Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-11-27
2003-12-30
Kim, Hong (Department: 2186)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C712S300000, C711S105000, C711S201000
Reexamination Certificate
active
06671219
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a binary data storage device. More particularly, the present invention relates to a technology that may be applied conveniently to a semiconductor storage device, such as a RAM (Random Access Memory) and a ROM (Read Only Memory), which is connected to a data processor such as a microprocessor or a microcomputer and to or from which data is written or read one byte (8 bits), one word (16 bits), and an integral multiple of 8 bits at a time.
BACKGROUND ART
As the operation frequency or the data processing power (number of data bits) of a microprocessor or a microcomputer that accesses a semiconductor storage device increases, there is a need for a higher-speed semiconductor storage device.
To satisfy this need, various technologies have been proposed to increase the speed of a semiconductor storage device. Examples of those technologies are found in JP-A-6-332793 or in IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS, PP. 190-201, 1999. However, the conventional technique to increase the speed of a semiconductor storage device has placed emphasis on device miniaturization or on the increase in speed of a memory cell circuit from which data is read. Those technologies do not take into consideration the relation with a data processor, such as a microprocessor or a microcomputer, to which the semiconductor storage device is connected.
Normally, the configuration of a semiconductor storage device is such that the read/write operation can be performed at a time for the number of data bits basically used by a data processor, such as a microprocessor or a microcomputer, connected to the semiconductor storage device. For example, a semiconductor storage device connected to a data processor whose basic data length is 32 bits is configured such that data is read or written efficiently 32 bits at a time. Similarly, a semiconductor storage device connected to a data processor whose basic data length is 64 bits is configured such that data is read or written efficiently 64 bits at a time.
Because an address is allocated to each byte (8 bits) of data in a common data processor, a semiconductor device connected to the data processor is designed to read and write data on an address number basis. In addition, for the read data length, the semiconductor storage device is designed so that data which is ½
n
times (n is an integer equal to or larger than 1) the basic data length and which is 8 bits or longer must be able to be read or written. That is, for the basic data length of 32 bits, 16 bits (32×½
1
bits), or 2 bytes, and 8 bits (32×½
2
bits), or 1 byte, must be able to be read or written. This will be described more in detail with reference to the drawings.
FIG. 3
schematically shows the physical array of data stored in a conventional semiconductor storage device connected to a data processor whose basic data length is 32 bits (4 bytes) and the logical operation executed when 32 bits of data is read from the storage device. The numeral
300
indicates data stored in the semiconductor storage device, and the numeral
301
indicates data read from the semiconductor storage device. In this case, 32 bits of data is read directly. That is, the semiconductor storage device is laid out and wired so that the relative distance between the nth bit of the data in the semiconductor storage device and the nth bit of the register into which the data is read becomes shortest.
FIG. 4
schematically shows the physical array of data stored in a conventional semiconductor storage device connected to a data processor whose basic data length is 32 bits (4 bytes) and the logical operation executed when 16 bits (2 bytes) of data are read from the storage device. The numeral
400
indicates data stored in the semiconductor storage device, and the numerals
401
and
402
indicate data read from the semiconductor storage device.
FIG.
4
(
a
) shows how the low-order 16 bits (byte
1
and byte
0
) of the data
400
are read, and FIG.
4
(
b
) shows how the high-order 16 bits (bytes
3
, byte
2
) of the data
400
are read. It should be noted that, in FIG.
4
(
b
), the bit shift operation is required for 16 bits, from the high-order 16 bits to the low-order 16 bits. In a conventional semiconductor storage device, the memory cell array is laid out in the data bit sequence. Therefore, to execute the operation shown in FIG.
4
(
b
), the data must be physically shifted 16 bits. That is, in FIG.
4
(
a
), the relative distance between the nth bit (0≦n≦15) of the semiconductor storage device and the nth bit (0≦n≦15) of the register into which data is read is shortest. On the other hand, in FIG.
4
(
b
), the relative wiring length becomes longer because the n′th bit (16≦n′≦31)of the semiconductor storage device is stored in the nth bit (0≦n≦15)of the register into which data is read. This lengthens the wiring length, increases the wiring load, reduces the read speed, and increases the power consumption.
FIG. 5
schematically shows the physical array of data stored in a conventional semiconductor storage device connected to a data processor whose basic data length is 32 bits (4 bytes) and the logical operation executed when 8 bits (1 byte) of data are read from the storage device. The numeral
500
indicates data stored in the semiconductor storage device, and the numerals
501
,
502
,
503
, and
504
indicate data read from the semiconductor storage device.
FIG.
5
(
a
) shows how the 8 bits corresponding to byte
0
of the data
500
are read, FIG.
5
(
b
) shows how the
8
bits corresponding to byte
1
of the data
500
are read, FIG.
5
(
c
) shows how the 8 bits corresponding to byte
2
of the data
500
are read, and FIG.
5
(
d
) shows how the 8 bits corresponding to byte
3
of the data
500
are read. It should be noted that the bit shift operation is required for 8 bits from byte
1
to byte
0
in FIG.
5
(
b
), that the bit shift operation is required for 16 bits from byte
2
to byte
0
in FIG.
5
(
c
), and that the bit shift operation is required for 24 bits from byte
3
to byte
0
in FIG.
5
(
b
), respectively.
In a conventional semiconductor storage device, a memory cell array is laid out in data bit sequence. Therefore, when executing operation as shown in FIG.
5
(
b
), FIG.
5
(
c
), or FIG.
5
(
d
), the 8-bit, 16-bit, or 24-bit physical shift operation must be executed, respectively. That is, as in FIG.
4
(
b
), the relative wiring length becomes longer. This layout lengthens the wiring from each memory cell to the selector, increases the wiring load, reduces the read speed, and increases the power consumption. In addition, because 24 bit-shift signal lines sometimes run in parallel in some part of the above example as shown in FIG.
16
(
a
), there are some problems; for example, the wiring area is increased, and the signal lines are so dense that they cause crosstalk between signal lines. On the other hand, there is another method in which data is always read into a register at memory access time, 32 bits at a time, and then only the necessary number of bits of the data are extracted by shifting the bits. However, this method requires a time for bit shift processing and thus reduces the read speed.
It is an object of the present invention to provide a storage device that solves the above problems, that reads or writes even data shorter than the basic data length, for example, reads 8 bits of data (that is, byte) speedily, and that requires less power.
It is another object of the present invention to provide a storage device that reduces an area occupied by the wiring and that minimizes the generation of crosstalk.
The above and other objects and the new features of the present invention will be made more apparent by the description in the specification and the accompanying drawings.
DISCLOSURE OF THE INVENTION
The overview of the typical contents of the present invention disclosed in this application will be described below.
That is, a stor
Koike Tsuyoshi
Mizoguchi Makoto
Shimazaki Yasuhisa
Kim Hong
Mattingly Stanger & Malur, P.C.
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