Storage registers with charge packet accumulation capability, as

Details Storage registers with charge packet accumulation capability, as Storage registers with charge packet accumulation capability, as

1987-03-04

1989-02-07

Munson, Gene M.

Electrical pulse counters, pulse dividers, or shift registers: c

Charge transfer device

Particular input or output means

357 24, G11C 1928, H01L 2978, H01L 2714, H01L 3100

Patent

active

048037109

ABSTRACT:
A CCD storage register for storing an area array of picture elements in a solid-state imager comprises a first set of charge transfer channels arranged in a parallel array with intervening spaces. Respective ones of a second set of charge transfer channels are located in spaces adjacent to the second set of charge transfer channels. Charge transfer stages in adjacent charge transfer channels in said first and second sets of charge transfer channels have corresponding charge storage sites between which connections for charge transfer can be made selectively. This allows shift and add procedures to be carried forward in the CCD storage register. The shift and add capability allows time-delay-integration procedures and true line interlacing procedures, as examples, to be carried forward in the CCD storage register.

REFERENCES:
patent: 4539597 (1985-09-01), Kinoshita et al.
patent: 4547677 (1985-10-01), Parker
patent: 4580155 (1986-04-01), Tsoi et al.
Masafumi Kimata et al., "A 480X 480 Element Image Sensor with a Charge Sweep Device" IEEE Int. Solid-State Circuits Conf., (2/85), Dig. Tech. Papers, pp. 100-101.
Sequin "Two-Dimensional Charge-Transfer Arrays" IEEE J. Solid-State Circuits vol. SC-9 (6/74) pp. 134-142.

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