Patent
1994-04-01
1996-12-31
Kim, Matthew M.
395449, 395467, 395491, G06F 1208
Patent
active
055903096
ABSTRACT:
A high performance cache and storage control and management scheme for storage protection (SP) bits. The SP bits of interest are "key", "reference" and "change" bits which are architected to prevent unauthorized access to storage and to allow the efficient paging of main storage data. Access to this SP cache (SPC) is achieved via a 5 cycle pipeline. This SPC pipeline will deliver information back to the requestor as well as manage updates to the SPC on cache hits. The pipeline leads to a request stack in the SP storage (SPS) controller. This SPS stack manages the request during its execution in the SPS and the subsequent putaway of fetch results in the SPC. The organization of the cache along with its integration of directory information allow for the utilization of the unique properties of SP data to provide an extremely fast and efficient cache management scheme.
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Bixler Jeffrey C.
Chencinski Edward W.
Christensen Neal T.
Augspurger Lynn L.
International Business Machines - Corporation
Kim Hong
Kim Matthew M.
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