Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-11-30
2001-08-21
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290, C365S185270, C365S185180, C365S185130, C365S185110, C365S185020
Reexamination Certificate
active
06278635
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a step-down circuit, particularly to a circuit for decreasing an external power source voltage supplied from the outside, and the present invention also relates to a semiconductor storage apparatus and a storage method, particularly to a semiconductor storage apparatus and a storage method for performing an operation of erasing data stored in the semiconductor storage apparatus and subsequently writing back a cell in an excessively erased state.
The present invention further relates to a storage method of a semiconductor storage apparatus, particularly to a storage method of a semiconductor storage apparatus for performing an operation of erasing data stored in the semiconductor storage apparatus and subsequently writing back the cell in the excessively erased state.
2. Description of the Prior Art
In order to achieve a low voltage operation in a flash memory, it is necessary to reduce a cell threshold value voltage after erasing, and various studies have been performed.
As a conventional data writing operation of the flash memory, there is known a channel hot electron (CHE) injection system comprising: applying a voltage of about 5 V to a selected bit line connected to a selected cell drain diffusion layer; applying a voltage of about 10 V as a high voltage to a selected word line connected to a selected cell control gate; and injecting an electron generated in a channel area (P well surface layer area between source and drain) in the vicinity of the drain diffusion layer into a floating gate (FG).
Moreover, with respect to data erasing, the erasing is performed (FN tunneling system) by applying a voltage of about 5 V to a substrate (or a source diffusion layer), applying a negative high voltage to all word lines or a selected word line (control gate), and extracting an electron accumulated in FG to the substrate (or the source diffusion layer).
After the erasing operation, by applying a voltage of about 5 V to the drain diffusion layer, applying a voltage of about 5 V to the control gate, injecting the electron to FG with respect to a cell in a depression state (excessively erased state), and performing a light writeback operation (compaction), a threshold value distribution of the cell in the excessively erased state is converged, and this operation is well known, and described, for example, in Japanese Patent Application No. 116660/1993. The aforementioned cell writing, erasing, and write-back operations are shown in FIG.
5
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When the compaction operation is performed in the aforementioned method, by repeatedly performing the operation, a gate insulating film in the vicinity of a drain side is loaded with a stress by electron injection in the compaction operation in addition to electron injection in the writing operation, the gate insulating film is easily deteriorated, and a problem occurs that the semiconductor storage apparatus lacks reliability.
SUMMARY OF THE INVENTION
1. Objects of the Invention
An object of the present invention is to provide a storage method of a semiconductor storage apparatus which can prevent deterioration of a gate insulating film by repeatedly performing data writing/erasing.
2. Summary of the Invention
There is provided a storage method of a semiconductor storage apparatus provided with a source/drain area formed in a semiconductor substrate, a floating gate formed on a top layer of the area via a gate insulating film, and a control gate formed on the floating gate via an interlayer insulating film, the method comprising steps of: applying a predetermined positive voltage to a bit line connected to the drain area and a word line connected to the control gate, injecting an electron to the floating gate, and writing data to a selected memory cell; applying a predetermined negative voltage to a gate line, applying the predetermined positive voltage to a common source line connected to the semiconductor substrate or the source area, discharging the electron accumulated in the floating gate of the selected memory cell, and performing data erasing; and after the data erasing, applying the predetermined positive voltage necessary for injecting the electron to the floating gate from a channel area in the vicinity of the source area to the common source line, and writing back the memory cell erased excessively.
REFERENCES:
patent: 5668759 (1997-09-01), Ohtsuki
patent: 5856944 (1999-01-01), Prickett, Jr. et al.
patent: 6006304 (1999-12-01), Mukai et al.
NEC Corporation
Tran Andrew Q.
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