Storage media reading system

Details Storage media reading system Storage media reading system

2001-01-24

2002-08-20

Edun, Muhammad (Department: 2653)

Dynamic information storage or retrieval

Control of storage or retrieval operation by a control...

Control of information signal processing channel

C369S060010

Reexamination Certificate

active

06438081

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a storage media reading system which can extract a sync clock signal for information reproduction and reproduced data from information recorded in the form of combinations of “1” and “0” in a digital versatile disc (DVD), a compact disc-read only memory (CD-ROM) or the like with use of such a phase-locked loop circuit as a phaselocked loop (PLL).
Recorded on an optical disc such as a DVD or CD-ROM are information or data in the form of combinations of logical values of “1” and “0”. For example, when the sync clock signal has a period of T, data is recorded in combinations of signal periods of 3T to 11T. Such data recorded on the optical disc is read out by a pickup and waveform-equalized by a preamplifier and digitized to generate a binary signal. In order to reproduce recorded data from the binary signal, the PLL circuit reproduces a sync clock signal on the basis of the binary signal, and the binary signal is used as reproduced data synchronized with the reproduced sync clock signal. At this time, synchronization is achieved in the PLL circuit so that an edge of the binary signal and a falling edge of the sync click signal (when the sync clock signal has a duty of 50%, the falling edge of the sync clock signal corresponds to a middle point between adjacent rising edges of the sync clock signal) are made to be coincided. Under this condition, when the binary signal is latched at a rising edge of the sync clock signal, a highest quality of reproduced data can be acquired.
The aforementioned technique is conventionally known and is valid when the duty of the sync clock signal is 50%. However, when the duty of 50% cannot be secured, the timing of rising or falling (level change) in the binary signal goes out of the middle point between adjacent edges of the sync clock signal. Under such a condition, a small jitter takes place in the sync clock signal or binary signal, the normal value of the binary signal cannot be latched, thus resulting possibly in that erroneous reproduced data is output. In order to realize a sync clock signal having a duty of 50%, it is usual to generate a clock signal of a frequency twice as high as a required frequency and frequency divide the generated clock signal. However, nowadays, it has become difficult to generate such a high frequency signal as a transfer rate is increased. A disc such as a DVD or CD-ROM is rotated at a high speed for the purpose of enabling high-speed access, and a data transfer rate tends to also be increased correspondingly.
It is also substantially difficult to forcibly make the timing of level change in the binary signal coincide with the timing of a middle point between adjacent edges of the sync clock signal, including logical gate delay or changes in the characteristics of circuit elements. It is difficult to predict fluctuations in the duty of a clock generated in the interior of an LSI or variations in the logical gate delay upon manufacturing it.
Disclosed in JP-A-
7
-221800 (laid-open on Aug. 18, 1995) is a technique for automatically adjusting the phase of an edge of a clock signal to be input to a data discriminating/reproducing circuit at a already-determined phase, wherein the values of input data for phases leading or lagging with respect to a reproduced clock signal are compared with the value of the input data for the phase of the reproduced clock signal, land the phase of the reproduced clock signal in a phase synchronization loop is automatically adjusted so that these data values become equal to each other. Since this technique is directed to adjustment of the phase of the reproduced clock signal per se. separately from the phase synchronization loop, however, a result of the phase adjustment does not accurately reflect even another clock signal having a phase difference given for the aforementioned comparison, and thus it is expected that, when a data transfer rate is high, it becomes difficult to perform the phase adjustment.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a storage media reading system which can generate a sync clock signal from a signal read out from a recording medium, can use the clock signal to reduce an error generated at the time of reproducing data, and can achieve a high quality of reproduction of digital data.
In accordance with an aspect of the present invention, there is provided a storage media reading system which comprises:
a phase detector having first and second input terminals, a binary signal obtained from data recorded on a recording medium and carrying the data being supplied to said first terminal;
a voltage controlled oscillator for generating (2m+1) multi-phase clock signals (m being a positive integer) which are changed in oscillation frequency according to an output of the phase detector and which are mutually shifted in phase by an integral multiple of 2&pgr;/(2m+1) and for extracting one of these multi-phase clock signals as a sync clock signal for data reproduction and for supplying part of the sync clock signal to the second input terminal of the phase detector;
a variable delay circuit for delaying the binary signal by a controllable delay time to generate a binary delayed signal; and
a delay control circuit including first circuits for determining a value of the binary delayed signal from the variable delay circuit in synchronism with the sync clock signal to generate a reproduced data signal and also including a second circuit for comparing a phase of the binary delayed signal from the variable delay circuit with phases of the multi-phase clock signals from the voltage controlled oscillator to generate a delay control signal to be supplied to the variable delay circuit for control of the delay time, and
wherein the reproduced data signal and sync clock signal are used to reproduce the data recorded in the recording medium.
In accordance with another aspect of the present invention, there is provided a storage media reading system which comprises a data reproducing circuit for reproducing a sync clock signal in a phase-locked loop circuit on the basis of a digital binary signal read out from a recording medium and for generating reproduced data through synchronization of the binary signal with the sync clock signal. The phase-locked loop circuit has a ring type voltage-controlled oscillator in its phase-locked loop which includes an odd number of delay gate stages whose delay times are determined by the phase comparison result. One of outputs of the delay gate stages is used as a sync clock signal fed back in the phase-locked loop. The data reproducing circuit further has a variable delay circuit for variably delaying the binary signal to generate a binary delayed signal and also has a delay control circuit for comparing the phase of the binary delayed signal from the variable delay circuit with phases of clock signals generated in the plurality of delay gate stages and for supplying the delay control signal to the variable delay circuit in such a manner that the binary delayed signal has a predetermined phase difference with respect to the sync clock signal.
In the aforementioned aspect of the present invention, the phase of the binary delayed signal to the sync clock signal is optimumly controlled on the basis of a phase relationship between the output clock signals from the delay gate stages present in the voltage controlled oscillator and the binary delayed signal. For example, the delay of the delayed signal from the variable delay circuit is controlled so that the timing of a level change in the delayed signal is away from a rising edge of the sync clock signal. As a result, when the duty of the sync clock signal is shifted from 50% as an increased data transfer rate causes n increased frequency of the sync clock signal, even generation of a jitter in the sync clock signal or binary signal enables a normal signal value to be latched by a latch circuit and thus accurate reproduced data corresponding to the binary signal to be obtained.
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