Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-09-15
2002-11-19
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S210000
Reexamination Certificate
active
06483363
ABSTRACT:
FIELD
The present invention relates generally to integrated circuits, and more specifically to integrated circuits having increased soft error rate tolerance.
BACKGROUND
Integrated circuits commonly include storage elements such as latches that retain state information and hold data. During a portion of a time cycle, or clock period, these storage elements hold data to be used during subsequent time cycles. When storage elements reliably retain data, computations can be error free. In contrast, when storage elements do not reliably retain data, computation errors can result.
Cosmic rays and charged particles can cause integrated circuits to be unreliable. When particles bombard portions of integrated circuits, localized areas of charge can build up on an integrated circuit die and cause stored information to be upset. For example, latches having transistors with diffusion regions can be susceptible to bombardment of charged particles. As particles bombard an integrated circuit die about a diffusion region held at a low voltage, the voltage can increase. Likewise, as particles bombard an integrated circuit about a diffusion region held at a high voltage, the voltage can decrease. When the bombardment is significant, the change in voltage in the diffusion region can cause the latch to change state, thereby causing a “soft error” to occur.
The addition of capacitance to a path-exclusive feedback node in a latch circuit is one known method for mitigating the above-described effects. Capacitance provides “capacity” to store a given amount of charge with less voltage change. One drawback of additional capacitance is reduced circuit speed. When the latch circuit changes state, the output voltage value changes, and the additional capacitance is charged as the voltage value changes. Although additional capacitance can reduce the latch circuit's susceptibility to soft errors, the speed of the latch circuit is reduced in part because the additional capacitance is charged as the voltage value changes.
FIG. 1
shows a prior art latch. Latch
100
includes forward inverter
118
and feedback inverter
110
cross-coupled together. Forward inverter
118
drives feedback node
114
which is input to feedback inverter
110
. Feedback inverter
110
in turn drives storage node
112
which is input to forward inverter
118
. Latch
100
passes data from data input node
102
to data output node
122
when pass gate
104
is closed. Pass gate
104
is closed when the clock signal on node
108
is high, and the inverse clock signal on node
106
is low. Latch
100
holds data when the clock signal on node
108
is low, and the inverse clock signal on node
106
is high.
When latch
100
is holding data, storage node
112
is at a stable logical state of either logical “1” or logical “0,” and buffer
120
drives data output node
122
. Forward inverter
118
receives the stored data value on storage node
112
, and drives feedback node
114
to the opposite logical state than that of storage node
112
. Feedback inverter
110
receives the opposite logical state on feedback node
114
, and drives storage node
112
with the original stored data value.
Capacitor
116
is coupled to feedback node
114
. When charge accumulates on feedback node
114
as a result of cosmic rays or other noise sources, capacitor
116
reduces the voltage variations for a given amount of charge, and reduces the likelihood of a soft error. Along with reducing the likelihood of a soft error, capacitor
116
acts as a low-pass filter, and reduces the speed with which feedback node
114
changes voltage. The addition of buffer (or inverter)
120
allows the data output node
122
to change voltage quickly without regard to the presence of capacitor
116
, but also consumes additional area and power.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved integrated circuit elements with reduced susceptibility to soft errors.
REFERENCES:
patent: 4806786 (1989-02-01), Valentine
patent: 5467038 (1995-11-01), Motley et al.
patent: 5654658 (1997-08-01), Kubota et al.
patent: 5821791 (1998-10-01), Gaibotti et al.
patent: 5973529 (1999-10-01), Chappell et al.
patent: 5982211 (1999-11-01), Ko
patent: 6002284 (1999-12-01), Hill et al.
patent: 6094385 (2000-07-01), Trimberger
Karnik Tanay
Vangal Sriram R.
Veeramachaneni Venkat S.
Callahan Timothy P.
Intel Corporation
Nguyen Linh
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Storage element with stock node capacitive load does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Storage element with stock node capacitive load, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Storage element with stock node capacitive load will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2961655