Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
1998-07-23
2001-06-26
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S504000, C382S240000
Reexamination Certificate
active
06252611
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a storage device and an access method and, more particularly, to a storage device and an access method which are preferably used in hierarchical coding which divides an image into a plurality of layers having different numbers of pixels.
2. Description of the Related Art
In one of the presently available coding methods, a high-definition image (bottom hierarchical or first layer data) is used to form image data of a second layer having a smaller number of pixels, the second layer image data is then used to form image data of a third layer having an even smaller number of pixels, and this process is repeated until image data of top layer is formed. This type of a coding method is called hierarchical coding, in which image data of each layer is presented on a monitor in accordance with respective definition (the number of pixels). A user thus watches the image data by selecting the image data, which matches the definition of the user's own monitor, out of the hierarchically coded image data.
The image data of one definition is treated as the bottom hierarchical (first) layer image data to form image data of higher layers sequentially. When all of these data are stored and transmitted as they are, extra memory capacity and extra data transmission capacity for the higher layer image data are additionally required compared with the case when the bottom layer image data only is stored or transmitted.
The inventors of this invention have already proposed a hierarchical coding method to restrict an increase in the memory capacity.
For example, suppose now that the sum of four pixels of 2×2 (rows×columns) is treated as a higher hierarchical pixel (a pixel value) in a hierarchical coding of three layers. Referring to
FIG. 9A
, 8×8 pixels are now considered as an image of the bottom hierarchical layer, and the sum m0 of the top left four pixels, 2×2 pixels, h00, h10, h01, and h11 is computed, and the sum m0 is then treated as the top left pixel in a second layer. In the same way, the sum ml of the top right four pixels h20, h30, h21, and h31, the sum m2 of the bottom left four pixels h02, h12, h03, and h13, and the sum m3 of the bottom right four pixels h22, h32, h23, and h33 in the bottom hierarchical layer are respectively computed, and these sums are respectively treated the top right, the bottom left and bottom right pixels in the second layer. The sum q0 of the four pixels m0, m1, m2, and m3 as 2×2 pixels in the second layer is computed, and the sum is a pixel of an image in the top hierarchical layer.
If the pixels h00 through h33, m0 through m3, and q0 are all stored, the extra memory capacity for the pixels m0 through m3 in the second layer and the pixel q0 in the third layer will be additionally required.
Referring to
FIG. 9B
, the pixel q0 in the third layer is positioned, for example, in place of the bottom right pixel m3, out of the second layer pixels m0 through m3. The second layer is thus constructed of the pixels m0 through m2 and q0.
Referring to
FIG. 9C
, the pixel m0 in the second layer is positioned, for example, in place of the bottom left pixel h11, out of the first layer pixels h00, h10, h01, and h11, all these used to determine the pixel m0 in the second layer. Similarly, the remaining pixels m1, m2, and q0 in the second layer are substituted for the pixels h31, h13, and h33 in the first layer. Although the pixel q0 is not directly derived from the pixels h22, h32, h23, and h33, the pixel q0 is substituted for the pixel m3 which is directly derived from these pixel, and the pixel q0 is thus positioned instead of the pixel m3 in place of the pixel h33.
In this way, referring to
FIG. 9C
, the total number of pixels is
16
of 4×4 pixels, and remains unchanged from the number of pixels in the bottom hierarchical layer shown in FIG.
9
A. An increase in the memory capacity is thus prevented.
The pixels m3 and h33, replaced with the pixel q0, and pixels h11, h31 and h13, respectively replaced with the pixels m0 through m2, are decoded as follows.
Since q0 is the sum of m0 through m3, equation q0=m0+m1+m2+m3 holds. The pixel m3 is determined from equation m3=q0−(m0+m1+m2).
m0 is the sum of h00, h10, h01 and h11, equation m0=h00+h10+h01+h11 holds. h11 is thus determined from equation h11=m0−(h00+h10+h01). Similarly, h31, h13, and h33 are determined. h33 is determined after the determination of m3.
In the above hierarchical coding, a delay circuit for line delay of the first layer pixel (pixel value) was conventionally required besides a general-purpose memory for storing the hierarchical coding results (such as SRAM (Static Random Access Memory) or DRAM (Dynamic RAM)).
For example, referring to
FIG. 9C
, equation h11=m0−(h00+h10+h01) needs to be computed to determine, in the first layer, the pixel h11, if h11 is not stored. Pixels h00 and h10 on a first line and pixels h01 and m0 on a second line are necessary to compute h11. Suppose that the image data is read from a memory line by line from top to bottom, and the computing of the pixel h11 has to wait for the line starting with h01, namely, wait for pixels m0, h00, h10, and h01 required to compute the pixel h11, with the line starting with h00 delayed by one line.
Besides the memory for storing the hierarchical coding results, the delay circuit for line delay of the image data is conventionally required, causing the device bulky.
OBJECT AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to make the device compact.
According to one aspect of the present invention, the storage device comprises a first memory which has addresses corresponding to pixels for input image data and a memory area of which is divided into a plurality of blocks, wherein the blocks are addressable on a block by block basis; an addressing module for concurrently addressing the blocks of the first memory according to, at least, first and second address signals; and a read and write module for concurrently reading from and writing to addresses, designated by the first and second address signals, in the blocks in the first memory.
According to another aspect of the present invention, the access method comprises the step of concurrently addressing the blocks in a memory according to, at least, first and second address signals and the step of performing concurrently reading from and writing to addresses, designated by the first and second address signals, in the blocks in the memory.
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L. Wang,Reduced-difference pyramid: a data structure for progressive image transmission, Optical Engineering, Jul. 1999, vol. 28, No. 7, pp 708-716.
Chauhan Ulka J.
Frommer William S.
Frommer & Lawrence & Haug LLP
Savit Glenn F.
Sony Corporation
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