Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2000-10-03
2002-03-26
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185330
Reexamination Certificate
active
06363009
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a storage device especially equipped with both two-valued memory to handle the binary logic and multivalued memory to handle three or more logical values.
2. Description of the Background Art
Flash storage media, each equipped with flash memories suitable for an increase in storage capacity as its memory elements, are commonly used as information storage devices. With the diversification of information, the flash storage media are required to meet two demands: further increase in storage capacity and speeding up of data transfer.
In terms of an increase in storage capacity, techniques of multivalued flash memories each handling three or more logical values have been proposed.
FIGS. 10A
,
10
B, and
10
C are cross-sectional views conceptually illustrating the operation of one of such flash memories. In
FIGS. 10A
to
10
C, for example, n-type source S and drain D are spaced from each other in the surface of a p-type semiconductor substrate T. Above the area between the source S and the drain D, a floating gate FG and a gate G, isolated from each other, are provided in that order.
FIG. 10A
shows the writing state wherein electrons (indicated by circled minus signs in the figures) are drawn into the floating gate FG from the surface of the semiconductor substrate T between the source S and the drain D. This is performed by the application of a positive voltage to the gate G. For two-valued flash memories, only a single kind of positive voltage is applied during a write operation and the writing state is set to be a “0” logic state. For multivalued flash memories such as the one handling four logical values, on the other hand, three kinds of positive voltages are set for application to the gate G and the writing state is set to either of logical values “10”, “00”, and “01” in descending order of positive voltage.
FIG. 10B
shows the erasing state wherein electrons are sent from the floating gate FG into the surface of the semiconductor substrate T between the source S and the drain D. This is performed by the application of a high negative voltage to the gate G. In this case, only a single kind of negative voltage is adopted irrespective of whether the flash memory is two-valued or multivalued type. The erasing state is set to a logical value “1” for two-valued flash memories and “11” for multivalued flash memories.
FIG. 10C
shows the reading state wherein a conductive channel is created between the source S and the drain D by the application of a voltage to the gate G. The threshold voltage in the writing state is higher than that in the erasing state.
FIG. 11
is a graph showing the distribution of the threshold voltage Vth of a two-valued flash memory and
FIG. 12
shows the same of a four-valued flash memory. In the two-valued flash memory, as shown in
FIG. 11
, the distribution of the threshold voltage Vth divides into two sections at a voltage V
0
. Thus, whether the logic state is “1” or “0” is determined or read out by applying the voltage V
0
to the gate G to see whether or not current flows between the source S and the drain D.
In the four-valued flash memory, on the other hand, the distribution of the threshold voltage Vth divides into four sections at three voltages V
1
, V
2
, and V
3
as boundaries as shown in FIG.
12
. Thus, by applying the three voltages V
1
, V
2
, and V
3
to the gate G, the logic state “10”, “00”, “01”, or “11” is read out.
The multivalued flash memories are suitable for an increase in storage capacity but not for an increase in transfer rate since its read operation requires a plurality of voltages. Conversely, the two-valued flash memory is suitable for rapid data transfer but not for large-capacity storage.
Now, data handled in such flash memories fall into two broad categories: management data including parameters necessary for internal processing in the flash storage media; and user data for use by users. The management data is read out in small different quantities over several times when a flash storage medium is accessed. Therefore, the reading speed for the management data impacts significantly on the transfer rate. On the other hand, it is preferable for the flash memories to handle the user data in large quantity.
The techniques for dividing data among two-valued and multivalued storage areas in a storage device are disclosed for example in Japanese Patent Application Laid-Open Nos. 11-31102 (1999) and 11-224491 (1999).
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a storage device comprising: a first storage area for reading a storage state with a single readout voltage; and a second storage area for reading a storage state with a plurality of readout voltages, wherein the first storage area stores management data and the second storage area stores user data.
According to a second aspect of the present invention, in the storage device of the first aspect, the first and second storage areas use independent individual physical addresses for storing the management data and the user data, respectively. The storage device further comprises: a CPU exercising overall control using universal physical addresses which handle all of the individual physical addresses in a uniform manner.
According to a third aspect of the present invention, in the storage device of the second aspect, the universal physical addresses each include a selection bit for use in determining in which of the first and second storage areas one of the individual physical addresses is to be used, and bits indicating the one of the individual physical addresses.
According to a fourth aspect of the present invention, in the storage device of the first aspect, the first and the second storage areas are associated with each other, the first storage area including a plurality of first storage areas and the second storage area including a plurality of second storage areas; corresponding ones of the first and second storage areas which are associated with each other form a single storage element based on a mapping of individual physical addresses, the first and second storage areas storing the management data and the user data, respectively, by the individual physical addresses; and each of the storage elements individually uses the individual physical addresses. The storage device further comprises: a CPU exercising overall control using universal physical addresses which handle all of the individual addresses in a uniform manner.
According to a fifth aspect of the present invention, in the storage device of the fourth aspect, the universal physical addresses each include a selection bit for use in determining in which of the first and second storage areas one of the individual physical addresses is to be used, and bits indicating the one of the individual physical addresses.
In accordance with the storage device of the first aspect, the management data requiring a rapid readout is stored in the first storage area which uses a single readout voltage for reading, while the user data requiring large storage capacity is stored in the second storage area which uses a plurality of readout voltages for reading. This increases data transfer rate and storage capacity.
In accordance with the storage device of the second and fourth aspects, the CPU can exercise overall control without considering in which of the first and second storage areas the management data or the user data is to be stored.
In accordance with the storage device of the third aspect, the universal physical address reflects in which of the first and second storage areas the individual physical address is to be used. This makes it easy to divide the management data and the user data to be received/transmitted among the first storage area and the second storage area.
In accordance with the storage device of the fifth aspect, the universal physical address reflects in which storage element the individual address physical is to be used. This makes it easy to divide the management data and the user
Mitsubishi Denki & Kabushiki Kaisha
Phan Trong
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