Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-02-18
2002-03-19
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S195000, C365S149000
Reexamination Certificate
active
06359830
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to integrated circuit write enable signal generating circuitry and methods for driving storage cells which we have found have a tendency to operate improperly if internal feedback in the storage cell turns off for an excessively long period. The invention relates more particularly to driving such cells with a write enable signal having a predetermined level which disables the cell feedback for no longer than a predetermined interval, even though the integrated circuit responds to differing clock frequencies.
BACKGROUND ART
FIG. 1
is a block diagram of a prior art programmable integrated circuit register including N identical storage cells
0
,
1
. . .
1
. . . (N−1), responsive to clock source
12
having approximately a 50% duty cycle. Clock source
12
drives cells
0
,
1
. . . i . . . (N−1) in parallel directly and via inverting driver
10
. Cells
0
,
1
. . . i . . . (N−1) are also respectively responsive to binary output bits
0
,
1
. . . i . . . (N−1) of input signal source
14
, write decode source
16
and read decode source
18
. A write operation of the bit from source
14
for a particular cell i occurs when write decode source
16
supplies a binary 1 to cell i during the low (ground voltage) half cycle of the inverted clock output of driver
10
. The write decode has a positive going transition that initiates the write operation about 100 ps after a positive going transition of clock source
12
, for an exemplary 1 GHz clock source. Sources
12
and
16
are synchronized to achieve this result so negative going transitions thereof occur simultaneously. A read operation of the bit which is stored in cell i occurs when read decode source
18
supplies a binary 1 to cell i during the low voltage half cycles of the output of clock source
12
so the read and write operations cannot occur at the same time.
The circuit of cell i, schematically illustrated in
FIG. 2
, includes a storage cell comprising two back-to-back, regeneratively connected inverters
20
and
22
which selectively have bit i of source
14
written into them. Each of inverters
20
and
22
includes a pair of complementary metal oxide semiconductor (CMOS) field effect transistors (FET) having series connected source drain paths. Inverter
20
is enabled only during the positive half cycle of the output of driver
10
while inverter
22
is enabled whenever the DC power supply terminals
28
and
30
are connected to +V
DD
and ground. Thereby, bit i from source
14
is stored in cell i at least during the positive voltage half cycles of the output of driver
10
. During the low voltage half cycles of the output of driver
10
, inverter
20
is disabled and bit i from source
14
can be written into cell i. Such writing occurs if bit i from write decode source
16
has a binary one (positive voltage) value.
To these ends, inverter
20
includes P channel FET
24
and N channel FET
26
, having source drain paths connected in series with each other. FETs
24
and
26
are selectively connected between +VDD power supply terminal or rail
28
and ground terminal or rail
30
via the source drain path of N-channel FET
32
, having a gate electrode tied to the output of driver
10
. FETs
24
and
26
have gate electrodes tied to each other and the output of inverter
22
. FETs
24
and
26
have drains tied to each other to form output terminal
33
of inverter
20
which drives the input of inverter
22
. Terminal
33
can be considered the storage node of cell i.
Inverter
22
has the same configuration as inverter
20
, thus includes complementary FETs
34
and
36
. The gate electrodes of FETs
34
and
36
are connected to be driven in parallel by the voltage at terminal
33
. The drains of FETs are connected to each other and the gate electrodes of FETs
24
and
26
. Terminal
33
is selectively coupled to bit i of input signal source
14
via the source drain path of N-channel FET
38
, having a gate electrode responsive to bit i of write decode source
16
.
During the half cycle of source
12
while the output of driver
10
is positive, the source drain path of FET
32
is ON, i.e., has a low impedance, to enable inverter
20
so cell i operates in a storage mode. Cell i operates in the storage mode because of the regenerative, positive feedback arrangement of inverters
20
and
22
.
To consider the operation of the cell of
FIG. 2
during a write operation, i.e., while driver
10
applies a low voltage to FET
32
to disable inverter
20
, assume that source
16
has a positive value to turn on FET
38
while source
14
has a positive value. Thereby, cell i stores a binary one voltage substantially equal to +V
DD
at terminal
33
. The high voltage remains at terminal
33
after source
16
turns off FET
38
. Similarly, cell i and terminal
33
are at a low substantially ground voltage in response to bit i having a low voltage value while source
16
turns on FET
38
. The voltage at terminal
33
remains low after source
16
turns off FET
38
. Hence, during the interval while the output of driver
10
is low to turn off FET
32
and disable inverter
20
, the voltage at terminal
33
follows the voltage coupled through the source drain path of FET
38
.
In response to bit i of write decode source
16
turning on FET
38
, which can occur only while FET
32
is off, the voltage at terminal
33
is substantially equal to the voltage bit i of signal source
14
supplies to the source of FET
38
. Because FET
32
turns on simultaneously with FET
38
turning off, cell i stores the value of bit i that source
14
supplied to the cell during the write operation.
If bit i of source
14
supplies a positive voltage, representing a binary one, to terminal
33
cell i stores the binary one even when inverter
20
is disabled by the low voltage output of driver
10
. This is because the positive voltage at terminal
33
turns on FET
36
and turns off FET
34
to drive FETs
34
and
36
substantially to ground. The ground voltage at the drains of FETs
34
and
36
turns on FET
24
, causing +V
DD
at terminal
28
to be regeneratively supplied to terminal
33
.
Writing a zero voltage to terminal
33
does not have a complementary effect because the resulting high voltage at the drains of FETs
34
and
36
turns off FET
24
and turns on FET
26
. Since FET
32
is turned off, the drains of FETs
24
and
26
float except for the connection thereof to terminal
33
. Hence, if bit i of write decode source
16
is zero when the output of driver
10
is low, the voltage at terminal
33
floats and is influenced significantly by stray charge coupled to terminal
33
.
Cell i stores a bit which is read during the half cycle of clock
12
while the output of clock source
12
has a low (i.e., ground) voltage, provided bit i of read decode source
18
has a high value. Thus cell i can be read only while the cell is in the storage mode and cannot be read while the cell is in the write mode. The read circuitry of cell i includes N-channel FETs
40
and
42
, and P-channel FET
44
. FETs
40
-
44
have source drain paths series connected between +V
DD
and ground DC power supply terminals
28
and
30
. FETs
40
,
42
and
44
have gate electrodes respectively tied to (1) terminal
33
, (2) the lead for output bit i of read decode source
18
and (3) the output terminal of clock source
12
. The read output terminal
46
of cell i is the common terminal for the drains of complementary transistors
42
and
44
.
During a read operation of cell i, the voltage at terminal
46
is the complement of the voltage at terminal
33
because FET
44
, when turned on, has a considerably higher source drain impedance than the combined source drain impedance of FETs
40
and
42
, when FETs
40
and
42
are turned on. Hence, if the voltage at terminal
33
is high while the low and high outputs of clock source
12
and bit i of source
18
respectively turn on FETs
44
and
42
, terminal
46
is pull
Fetzer Eric S
Naffziger Samuel D
Renstrom Preston J
Hewlett--Packard Company
Le Vu A.
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