Metal working – Barrier layer or semiconductor device making – Barrier layer device making
Reexamination Certificate
2002-11-12
2004-08-10
Thompson, Craig A. (Department: 2813)
Metal working
Barrier layer or semiconductor device making
Barrier layer device making
C257S068000
Reexamination Certificate
active
06773467
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a storage capacitor of a planar display and a process for fabricating the storage capacitor, and more particularly to a storage capacitor applied to a top gate thin film transistor liquid crystal display (TFT-LCD) and a process for fabricating the same.
BACKGROUND OF THE INVENTION
Nowadays, LCD has been applied to many fields of applications such as cellular phones, digital still cameras (DSCs), digital video cams (DVCs), camcorders, global positioning systems (GPSs), personal digital assistances (PDAs), personal computers (PCs), notebooks, and televisions (TVs). LCD has been playing an important role and acting as developing trend in the future with far more characteristics and advantages like thinness, low energy consumption, high resolution, high lightness, etc. Among many kinds of LCDs, TFT-LCD is so far the most popular planar display. Please refer to
FIG. 1
which is a circuit diagram showing one pixel cell of a TFT-LCD. This pixel cell mainly consists of a switching unit (TFT)
11
, a LCD unit
12
, and a storage capacitor
13
. The storage capacitor
13
is electrically connected to the LCD unit
12
in parallel to compensate the charge storage capacity of the LCD unit
12
which is also of a capacitor structure. Otherwise, the voltage of the LCD unit
12
may fall undesirably significantly due to voltage leakage after turning off the switching unit
11
.
A low temperature polysilicon (LTPS) process is developed for manufacturing the TFT array of the LCD. The low temperature polysilicon has the characteristic of faster electron mobility than the amorphous silicon (a-Si) over 100 times. That explains why each pixel of low temperature polysilicon has faster response time and smaller outlined dimension comparing with amorphous silicon.
FIG. 2
shows the conventional process for manufacturing a top gate LTPS-TFT on a glass substrate via a complementary metal-oxide-semiconductor (CMOS) manufacturing process. Please refer to FIG.
2
(
a
). A buffer layer
21
(e.g. a silicon dioxide layer) and an intrinsic amorphous silicon (i-a-Si) layer are formed on the glass substrate
20
. The intrinsic amorphous silicon layer is transformed into an intrinsic polysilicon (i-p-Si) layer
22
by a laser crystallization process. After the micro-photolithography and etch steps, the first intrinsic polysilicon structure
221
, second intrinsic polysilicon structure
222
, and third intrinsic polysilicon structure
223
are formed, as illustrated in FIG.
2
(
b
), and later provided as parts of n-channel TFT, p-channel TFT, and storage capacitor, respectively.
A photoresist layer is then deposited on the resulting strcuture of FIG.
2
(
b
). Afterwards, a micro-photolithography process is performed to form masks
23
on the first polysilicon structure
221
and second polysilicon structure
222
. Further referring to FIG.
2
(
c
), an n
+
-doping step is performed on the polysilicon layer with the mask of the photoresist
23
to define the source/drain regions
2211
of the n-channel TFT and the lower electrode
2231
of the storage capacitor. After removing the photoresist masks
23
, an insulating layer (e.g. silicon dioxide layer) is applied to the resulting structure to form a gate insulator layer
24
as shown in FIG.
2
(
d
).
Please refer to FIG.
2
(
e
). After sputtering a gate metal layer on the gate insulator layer
24
, the gate metal layer is patterned and etched to form a gate metal structure
251
and the upper electrode
252
of the storage capacitor. Then, the gate metal structure
251
serves as a mask for a following lightly n
−
-doping step to form a lightly doped drain structure
2212
. Afterwards, another photoresist layer is applied to the resulting structure and patterned and etched to form masks
26
on the n-channel TFT region and the storage capacitor region. A p
+
-doping step is then performed to form the source/drain electrodes
2221
of the p-channel TFT region, as shown in FIG.
2
(
f
).
After removing the photoresist masks
26
, an inter-layer dielectric layer
27
is provided, and a plurality of contact holes
28
are created by penetrating through the dielectric layer
27
at appropriate positions, as shown in FIG.
2
(
g
). Then, a metal layer is deposited by sputtering to fill the contact holes
28
, and patterned and etched to form gate contact structures
290
, source/drain contact strictures
291
, and electrode contact structures
292
of the storage capacitor. In the above structure, the lower electrode
2231
of the storage capacitor is made of highly doped n
+
-polysilicon and has excellent conductivity. Therefore, the capacitance provided by the lower electrode
2231
and upper electrode
252
is enough for most situations.
For some cases where the presence of the LDD stricture is not critical, the above process will be cost-inefficient. Therefore, other processes omitting the relating steps of the LDD structure are developed to reduce the production cost. One of the examples is illustrated with reference to FIGS.
3
(
a
) and
3
(
b
). After the steps similar to the ones illustrated with reference to FIGS.
2
(
a
) and
2
(
b
) are performed, a gate insulator
24
(e.g. silicon dioxide layer) and a gate metal layer are applied to the resulting structure. A photolithography process is executed to pattern the gate metal layer and thus form the gate structures
35
,
36
and upper electrode
37
on the intrinsic polysilicon structure
221
,
222
, and
223
, respectively. The gate structures
35
and
36
have smaller size than the first and second intrinsic polysilicon structures
221
and
222
, and the upper electrode
37
is smaller than the lower electrode
223
. Afterwards, a photoresist layer is deposited and patterned to form a mask
38
on the second intrinsic polysilicon structure
222
. Then, an n
+
-doping procedure is performed on the portion exposed from the mask
38
to define the source/drain electrodes of the n-channel TFT. The following procedures are similar to those shown in FIGS.
2
(
f
) to
2
(
h
) and will not be described again herein.
In this process, the upper electrode
37
is formed prior to the n
+
-doping procedure. Due to the shield of the upper electrode
37
, as shown in FIG.
3
(
b
) or
3
(
c
), the lower electrode
223
cannot be well defined by the n
+
-doping procedure. Therefore, the conductivity of the storage capacitor is not satisfactory.
Occasionally, essentially one of the n-channel TFT or the p-channel TFT is required and thus formed in the TFT matrix. FIGS.
4
(
a
) and
4
(
b
) show an exmaple that only the p-channel TFT is formed. The steps and numeral references are similar to those shown in FIGS.
3
(
a
) and
3
(
b
) except that the steps specific to the n-channel TFT region are omitted. Along with the p
+
-doping step for forming the source/drain electrodes of the p-channel TFT, the polysilicon structure
223
is doped to form the lower electrode of the storage capacitor. The following procedures are similar to those shown in FIGS.
2
(
g
) and
2
(
h
) and will not be described again herein. Due to the shield of the upper electrode
37
, the lower electrode cannot be well defined by the p
+
-doping procedure. Therefore, the conductivity of the storage capacitor is not satisfactory.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a storage capacitor structure having improved capacitance.
Another object of the present invention is to provide a process for fabricating a storage capacitor having improved capacitance.
A first aspect of the present invention relates to a storage capacitor of a planar display. The storage capacitor includes structures of a substrate; a lower electrode formed on the substrate and made of a semiconductor material; an insulator layer formed on the lower electrode; and an upper electrode formed on the insulator layer and having a dopant passage therein for allowing dopants to penetrate therethrough to reach the lower electrode. The storage capaci
Thompson Craig A.
Toppoly Optoelectronics Corp.
Volpe and Koenig P.C.
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