Storage capacitor in a liquid crystal display in which the...

Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal

Reexamination Certificate

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C349S039000, C349S145000, C349S143000

Reexamination Certificate

active

06285418

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) having a storage capacitor. More specifically, the present invention relates to improving the image quality of an LCD device by reducing the fluctuations in the capacitance of the storage capacitor.
2. Discussion of the Related Art
A thin film transistor (TFT) LCD includes TFTs functioning as switching devices, capacitors including liquid crystals between an upper plate electrode and a lower plate electrode, subsidiary capacitors, gate lines, and data lines.
For driving a TFT-LCD, a signal voltage is applied to a gate electrode, the TFT then turns on so that a data signal with image data is transmitted to the liquid crystals through the TFT. In the above-described case, the liquid crystals in the capacitor are charged. Ideally, the total electric charge that is stored in the liquid crystals remains constant until the next signal is applied.
However, the liquid crystal voltage varies due to the existence of various sources of capacitance by an amount &Dgr;V, which is expressed by the following approximate formula. &Dgr;V=Cgd*Vg/(Cgd+CLC+Csto), where &Dgr;V is the maximum amount of variation of the liquid crystal voltage, Cgd is the parasitic capacitance due to the overlap between gate and drain electrodes, CLC is the liquid crystal voltage, Csto is the capacitance of a storage capacitor, and Vg is the voltage of the gate electrode. The existence of &Dgr;V causes distortion in the liquid crystal voltage and is the primary reason for flickering in the LCD. To decrease &Dgr;V, it is preferable to increase the capacitance of the storage capacitor Csto.
FIG. 1
is a layout view of a LCD having a gate storage capacitor according to the related art.
FIG. 2
is a cross-sectional view of the LCD of FIG.
1
. Referring to FIG.
1
and
FIG. 2
, a pixel is defined on a substrate
100
by the intersection of the gate line
11
L and data line
15
L. A gate electrode
11
G is connected to the gate line
11
L, a source electrode
15
S is connected to the data line
15
L, and a drain electrode
15
D is arranged so as to oppose the source electrode
15
S. An active layer
13
is overlapped with the above-mentioned three electrodes and constitutes a TFT for use as a switching device. A pixel electrode
17
is connected to the drain electrode
15
D and covers the pixel area.
A gate storage capacitor is provided by a portion of the gate line
11
L, a portion of the pixel electrode
17
which is overlapped with the gate line
11
L, another portion of the gate line
11
L, and a subsidiary electrode
18
that is overlapped with a portion of the gate line
11
L.
For the sake of explanation, in the present specification, a storage capacitor will be defined by the subsidiary electrode
18
and a portion of the gate line which is overlapped by the subsidiary electrode
18
.
In the related art, a structure of the storage capacitor includes a gate line
11
L for defining a first electrode of a storage capacitor on a substrate
100
, and a gate insulating layer
12
disposed on an exposed surface of the substrate
100
including the gate line
11
L, a subsidiary electrode
18
, which is made of a metal that is used to form the source/drain region, disposed on the gate insulating layer
12
. A passivation layer
14
covers the subsidiary electrode
18
, and a contact hole is provided in the passivation layer
14
and exposing a portion of the subsidiary electrode
18
. A pixel electrode
17
is connected to the subsidiary electrode
18
through the contact hole that is provided in the passivation layer
14
.
The capacitance of the storage capacitor is expressed as ‘C∝A/d’, where A is the overlapped area between the subsidiary electrode and the gate line, which defines the two electrodes of the storage capacitor, and d is the thickness of the gate insulating layer, which defines the dielectric layer between the electrodes.
However, in the above-described related art structure, the subsidiary electrode is made by patterning a conductive layer for the source/drain region via a photolithography process. In carrying out the photolithography process, the position of the subsidiary electrode
18
may vary due to process errors such as misalignment of the photo mask, or the exposure, or the etchant, or other reasons.
Note that when the overlapped width between the subsidiary electrode
18
and gate line
11
L is defined, d
1
is set, and the overlapped width becomes equal to or less than d
1
since the subsidiary electrode
18
may move due to manufacturing deviations. Because the capacitance fluctuates greatly due to manufacturing deviations, the subsidiary electrode
18
is designed to be small so as to compensate for the manufacturing deviations. Thus, the capacitance of the storage capacitor is reduced because of the reduction in the overlapped area between the subsidiary electrode
18
and the gate line
11
L. Accordingly, the conventional LCD has very poor image quality due to flickering and other image defects.
SUMMARY OF THE INVENTION
To overcome the problems described above, preferred embodiments of the present invention provide a LCD having improved gate line patterns of a storage capacitor to reduce fluctuations in the liquid crystal voltage and improve the image quality.
A preferred embodiment of the present invention includes a substrate, a gate line on the substrate, a gate insulating layer covering the gate line, and a storage capacitor electrode on the gate insulating layer, wherein the storage capacitor electrode is arranged to overlap an entire width of the gate line, and wherein the gate line includes a straight line portion and a recessed portion.
In another preferred embodiment of the present invention there is provided a substrate, a gate line on the substrate, the gate line including a gate electrode protruding towards a first direction, a straight region, and a recessed region protruding towards a second direction opposite of the first direction, a data line crossing with the gate line, the data line including a source electrode, a drain electrode arranged such that the drain electrode opposes the source electrode, a storage capacitor electrode overlapped with the recessed region of the gate line, and a pixel electrode connected to the drain electrode.
Therefore, preferred embodiments of the present invention maximize the area of overlap between the gate line and the subsidiary electrode in order to maximize the capacitance of the storage capacitor so that the variance in the capacitance of the storage capacitor due to manufacturing deviations is greatly minimized. Accordingly, the problems related to the related art, namely, flickering and poor image quality, are overcome by preferred embodiments of the present invention.
Other details, features, elements and advantages of the present invention will be described in detail below with reference to preferred embodiments of the present invention and the attached drawings.


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patent: 58 106860 (1983-06-01), None

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