Storage arrangement having a pair of RAM memories selectively co

Static information storage and retrieval – Addressing – Plural blocks or banks

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36523004, 36518904, 364200, 364900, G11C 700, G11C 800, G06F 1200, G06F 1300

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active

048932795

ABSTRACT:
A storage device capable of being configured either as a single-access memory or as two separate memories is described. The storage device is especially suited for use in a digital signal processor performing numeric algorithms such as fast fourier transforms, autocorrelation and digital filtering because certain of such algorithms require fast dual access to two correlated, but separate, parameters while other such algorithms require fast single access to identical parameters. The storage device is shown in an exemplary embodiment empolying a multiplexer to affect writing of data from either of two data busses to one of the memories. In a second embodiment the write port of the memory is connected to one bus and the read port is connected to both busses. In this embodiment a dual-port address register file and a pair of address generation units provide indirect addressing capability for the storage device. Method of operating separate memories in a single-access or a dual-access mode is also described.

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SYS DISGN/Memory SYSs, Computer Design, Aug. 1, 86, "Fi Fo RAM Controller Tackles Deep Data Buffering", by Tom Pai, pp. 109-112.

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