Storage-annealing plated CU interconnects

Details Storage-annealing plated CU interconnects Storage-annealing plated CU interconnects

1998-11-02

2001-05-08

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S692000, C438S694000, C438S700000, C438S702000

Reexamination Certificate

active

06228768

ABSTRACT:

TECHNICAL FIELD
The present invention relates to semiconductor devices comprising copper (Cu) or Cu alloy interconnection patterns. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnect structures.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed interdielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines formed in trenchs which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor “chips” comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via opening is typically formed by depositing an interdielectric layer on a conductive layer comprising at least one conductive pattern, forming an opening in the interdielectric layer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interdielectric layer can be removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via opening section in communication with an upper trench opening section, and filling the opening with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line. High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and the cross-sectional areas and distances between interconnects decrease, the RC delay caused by the interconnect wiring increases. Thus, the interconnection pattern limits the speed of the integrated circuit. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.18 micron and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs. Moreover, as line widths decrease, electrical conductivity and electromigration resistance become increasingly important.
Cu and Cu alloys have received considerable attention as a replacement material for Al in VLSI interconnection metallizations. Cu is relatively inexpensive, easy to process, has a lower resistivity than Al, and has improved electrical properties vis-à-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring. An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP, as in Teong, U.S. Pat. No. 5,693,563. However, due to Cu diffusion through the dielectric interlayer, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium tungsten (TiW), and silicon nitride (Si
3
N
4
) for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
Electroless plating and electroplating of Cu and Cu alloys offer the prospect of low cost, high throughput, high quality plated films and efficient via, contact and trench filling capabilities. Electroless plating generally involves the controlled autocatalytic deposition of a continuous film on the catalytic surface by the interaction in solution of a metal salt and a chemical reducing agent. Electroplating comprises the electrodeposition of an adherent metallic coating on an electrode employing externally supplied electrons to reduce metal ions in the plating solution. A seed layer is required to catalyze electroless deposition or to carry electric current for electroplating. For electroplating, the seed layer should be continuous. For electroless plating, very thin catalytic layers, e.g., less than about 100 Å, can be employed in the form of islets of catalytic metal. Suitable seed layer can comprise Cu itself or an alloy of Cu and any of various alloying elements, such as magnesium (Mg), Al, zinc (Zn), zirconium (Zr), tin (Sn), nickel (Ni), palladium (Pd), silver (Ag) or gold (Au). The seed layer can be sputter deposited or deposited by CVD.
There are, however, significant problems attendant upon conventional Cu interconnect methodology. Deposited Cu and Cu alloys, particularly Cu and Cu alloys deposited by electroless plating or electroplating, undergo self-annealing at room temperature. See Ritzdorf et al., “Self-Annealing of Electrochemically Deposited Copper Films in Advanced Interconnect Applications,” International Interconnect Technology Conference (IITC), June 1998, pp. 166-168, sponsored by the IEEE Electron Device Society. Such self-annealing causes recrystalization, a reduction in the resistivity of the deposited Cu or Cu alloy at room temperature by up about 20%, internal stresses and a significant reduction in hardness, e.g., up to about 40%. The Cu self-annealing phenomenon impacts subsequent processing in various ways.
For example, the significant reduction in hardness due to Cu self-annealing causes greater dishing during CMP requiring redesigning CMP parameters. Moreover, conventional practices comprise depositing Cu or Cu alloy, as in one or more damascene openings formed in dielectric layer, on a plurality of wafers and subsequently performing CMP to obtain a planarized surface. Between deposition, such as electroless plating or electroplating, and CMP, the wafers can be processed immediately or, depending upon the production situation at the time, stored in a storage area prior to CMP. As a result, wafers subsequently processed by CMP exhibit different polishing rates depending upon the period of time they were stored at room temperature subsequent to electroplating or electroless plating, during which varying degrees of self-annealing occurred. The difference in polishing rates results in non-uniform CMP, thereby leading to non-uniformities in subsequent metallization levels.
There exists a need for methodology enabling CMP of deposited Cu and Cu alloy layers for copper interconnects with hi

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