Storage addressing error detection circuitry

Details Storage addressing error detection circuitry Storage addressing error detection circuitry

1987-11-12

1990-02-20

Shaw, Gareth D.

Boots, shoes, and leggings

3642653, 3642467, 3649691, G06F 1200

Patent

active

049031945

ABSTRACT:
Storage addressing error detection circuitry detects addressing errors in a computer system during data transfers between an I/O unit and main storage where main storage has logical boundaries which if crossed can cause destruction of data. The central processing unit (CPU) of the computer system furnishes the I/O unit the starting address for the data transfer and thereafter the I/O unit furnishes addresses for completion of the data transfer. The starting address contains a hash value related to the logical boundaries. Each time the I/O unit presents an address with a hash value for a data transfer another hash value is generated from the remainder of the address passed by the I/O unit. If the two hash values do not compare equal, a logical boundary in main storage would be crossed and to prevent such an occurrence the storage operation is inhibited and an error signal is sent to the I/O unit which then terminates the data transfer. A write to a read only storage area is also detected as a storage addressing error. A write hash is a read hash inverted. The read hash would not compare equal to the write hash and an error signal would be generated and sent to the I/O unit if the I/O unit were attempting to write into a read only storage area.

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patent: 4524427 (1985-06-01), Vidalin et al.
patent: 4545016 (1983-01-01), Berger
patent: 4742447 (1988-05-01), Duvall et al.
patent: 4747044 (1988-05-01), Schmidt et al.
patent: 4750177 (1988-06-01), Hendrie et al.
patent: 4751703 (1988-06-01), Picon et al.

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