Stop/restart latch

Details Stop/restart latch Stop/restart latch

1988-02-16

1990-01-09

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307511, 307234, 3072721, H03K 1716, H03K 1902, H03K 3284

Patent

active

048930342

ABSTRACT:
The logic circuit is disclosed. Even if the system is stopped while an output latch circuit is in the latching state, when an input latch circuit is latching an input signal, the logic gate remains in the precharge mode, whereas the precharge signal as generated by a precharge signal generator circuit is in the "H" level, i.e. a precharge level. Therefore, the logic output from the logic gate is never erased. Within a period that the input and output latch circuits are both in the latching state, the system can be stopped without erasing the logic output.

REFERENCES:
"A 40 ns CMOS E.sup.2 PROM" Stewart and Plus, IEEE IS SCC 82/Thursday, Feb. 11, 1982.

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