Stitching design rules for forming interconnect layers

Details Stitching design rules for forming interconnect layers Stitching design rules for forming interconnect layers

1999-05-20

2001-05-01

Young, Christopher G. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Including control feature responsive to a test or measurement

C430S005000, C430S022000

Reexamination Certificate

active

06225013

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods of forming photoresist masks for a semiconductor process. More specifically, the present invention relates to methods for forming photoresist masks using stitching techniques.
BACKGROUND OF THE INVENTION
During semiconductor processing, an interconnect layer is typically formed as follows. A conductive layer (e.g., polysilicon, metal
1
, metal
2
, etc.) is blanket deposited over an upper surface of a wafer. A layer of photosensitive material (i.e., photoresist) is then deposited over the upper surface of the conductive layer. The photoresist is exposed to illumination through a reticle. The reticle includes a pattern of opaque and transparent areas that define a desired pattern of the conductive layer. The exposed portions of the photoresist layer undergo a chemical change which enables these exposed portions to be removed by a developing solution, while the unexposed portions of the photoresist layer are largely unaffected by the developing solution. After the developing step is completed, a pattern of photoresist remains over the conductive layer. The photoresist pattern defines the desired pattern of the conductive layer. An etch is then performed to remove the exposed portions of the conductive layer, thereby patterning the conductive layer. The photoresist pattern is then removed.
A typical wafer has a diameter of about 150 mm. Conventional wafers can also have other diameters, such as 200 mm or 300 mm. A conventional reticle can have a maximum field of exposure of 20 mm by 20 mm with a minimum feature size of 0.5 microns (or less) on the wafer. Other conventional reticles can have other maximum fields of exposure, such as 22×22 mm or 33×25 mm. The field of exposure is defined as the photoresist area exposed through the reticle at one time. Thus, to expose the entire photoresist layer, the reticle is sequentially exposed, moved (i.e., stepped) to an adjacent area, and then exposed again. A stepper device is provided to move the reticle between exposures. Because each die fabricated on the wafer typically has an area of less than 20 mm by 20 mm, the reticle includes the pattern(s) for an integer number of dice.
FIG. 1
is a top view of a wafer
100
that includes a plurality of dice
101
-
123
. In this case, reticle
125
is exposed one time for each of dice
101
-
123
. Thus, reticle
125
is exposed and stepped twenty three times to complete the patterning of dice
101
-
123
. The pattern on reticle
125
is typically 4 to 5 times larger than the desired dimension on the wafer, depending on the type of stepper device. The stepper device optically shrinks the pattern on the reticle, thereby providing an exposed pattern on the wafer that has the desired dimension. The ratio of reduction is fixed for a specific stepper, and cannot be changed.
A mask aligner is a different exposure tool, which exposes a mask having dimensions equal to the dimensions of the wafer. The mask aligner does not shrink the pattern of the mask. Thus, the dimensions of the pattern of the mask are identical to the dimensions of the exposed pattern on the wafer. The mask aligner is capable of simultaneously exposing a pattern over the entire upper surface of a wafer. However, a mask aligner undesirably results in a larger minimum feature size, typically on the order of about 1.2 microns or greater.
It would be desirable to create an interconnect structure having an area greater than 20 mm×20 mm with a minimum feature size of 0.5 microns (or less). One product that would benefit from such an interconnect structure is an image sensor for a digital still camera. Digital still cameras require an ultra-high resolution image sensor to produce pictures with a quality similar to, or higher than, that achieved by conventional 35 mm film-based cameras. To achieve high resolution, image sensors require a large number of pixels on a single chip. Placing a large number of pixels on a single chip requires a relatively large chip. (Note that it is not practical to reduce the pixel size beyond a certain point, as this would require focusing light using high quality lenses. Such lenses cost an order of magnitude more than standard lenses used today, leading to higher system cost.) The size of the chip, however, is limited by the field of exposure of the photolithography equipment used to pattern the interconnect structures of the chip. As described above, modern stepping photolithography equipment has a fixed, relatively small field of exposure. The desirable die size of an image sensor far exceeds the limited field of exposure of conventional photolithography equipment. An improved solution is therefore required to enable the exposure of a die having an area greater than the field of exposure of the photolithography equipment.
It would therefore be desirable to have a method for patterning an interconnect layer having a relatively small minimum feature size (i.e., 0.5 microns or less), wherein the interconnect layer is patterned over an area that is larger than the standard field of exposure of a reticle.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides improved methods for stitching a plurality of mask regions to form a large interconnect structure. Each of the mask regions has a relatively small minimum feature size (e.g., 0.5 microns or smaller). Stitching the mask regions together advantageously enables the fabrication of a relatively large interconnect structure having a relatively small minimum feature size. In one embodiment, the mask regions to be stitched are formed on a single reticle. Alternatively, the mask regions to be stitched can be formed on a plurality of separate reticles.
One improved stitching process includes the steps of (1) defining cut regions on the mask regions, wherein the cut regions are located immediately adjacent to the edges of the mask regions to be stitched, (2) implementing a first set of design rules in the cut regions, and (3) implementing a second set of design rules outside of the cut regions. The first set of design rules is selected to ensure that the stitching process results in the formation of acceptable interconnect traces in the cut regions. The first set of design rules is advantageously limited to relatively small areas of the mask regions (i.e., the cut regions). The second set of design rules is a conventional set of design rules used when forming a reticle. The second set of design rules is used for a large area of the mask regions (i.e., outside the cut regions).
In one embodiment, the first set of design rules specifies that trace patterns of the mask region are wider in the cut regions than outside of the cut regions. This ensures that the resulting interconnect traces have an adequate width in the cut regions.
In another embodiment, the first set of design rules specifies that trace patterns of the mask region are spaced further apart in the cut regions than outside of the cut regions. This ensures that the resulting interconnect traces have adequate line-to-line spacing in the cut regions.
In another embodiment, the first set of design rules specifies that trace patterns of the mask region must cross the cut region in a perpendicular manner. This advantageously simplifies the stitching process.
In yet another embodiment, the first set of design rules specifies that an interconnect can be formed entirely within the cut region (i.e., in parallel with the cut region. This advantageously increases the different types of interconnect traces that can be fabricated in accordance with the present invention.
The present invention also includes a stitching method that includes the steps of (1) defining a cut line on a first mask region and a second mask region, wherein the first mask region and the second mask region are stitched together on a wafer along the cut line, (2) aligning the cut lines of the first and second mask regions such that transparent regions of the first and second mask regions have a controlled amount of overlap with respect to the cut line, and (

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