STI scheme to prevent fox recess during pre-CMP HF dip

Details STI scheme to prevent fox recess during pre-CMP HF dip STI scheme to prevent fox recess during pre-CMP HF dip

2002-02-01

2004-01-06

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S433000

Reexamination Certificate

active

06673695

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for selective and controlled oxide removal as part of a process for the creation of Shallow Trench Isolation regions in the surface of a substrate.
(2) Description of the Prior Art
The art of creating semiconductor devices has over the years progressed in implementing improved device performance by reducing device feature dimensions and by creating semiconductor devices and packages of sharply increased densities. With these increased device densities, the challenge of providing adequate isolation of the created semiconductor devices takes on increased significance. Typically, the isolation of semiconductor devices is accomplished by creating shallow trenches in the surface of the substrate over which the devices are created and filling the created trenches with an isolation material such as silicon oxide and the like. The completed and filled trenches are commonly referred to as Shallow Trench Isolation (STI) regions in the surface of the substrate.
It is a requirement of creating STI regions in the surface of a substrate that the STI isolation material that is deposited in the created STI trenches is evenly distributed through the trenches in uniform density and has a surface of good planarity. This requirement must be maintained even for applications where the density of the created trenches varies over the surface of the substrate, resulting in significantly different absorption rates for densely spaced trenches when compared with widely spaced trenches. Inter-device isolation requirements may also vary, resulting in the creation of trenches of non-uniform width, which again places added burden on creating STI regions of good performance characteristics. A planar surface of STI regions after STI oxide fill is typically achieved by polishing the surface of the completed STI regions using methods of Chemical Mechanical Polishing (CMP) or methods of resist etch-back, reactive ion etching (RIE). The high degree of planarity of the surface of the STI region is required since the STI region is one of the first features that is created for a semiconductor device. Poor planarity of the surface of the STI regions therefore makes the maintenance of planarity throughout the steps of creating a complete device increasingly more difficult.
Conventional methods of creating STI regions in the surface of a substrate typically follow the sequence of first depositing a layer of pad oxide over the surface of a substrate after which a layer of etch stop material is deposited over the surface of the layer of pad oxide. The layers of pad oxide and etch stop material are patterned and etched, exposing the surface of the substrate where trenches for the STI regions are to be created. After the trenches for the STI regions have been etched in the exposed surface of the substrate, a layer of STI oxide is deposited over the surface of the etch stop layer, filling the created trenches. The etch stop layer is then removed, exposing the surface of the layer of pad oxide. The final step requires that the layer of STI oxide, which at this time protrudes above the surface of the substrate, is reduced in height, which is typically achieved by exposing the surface of the STI oxide, including the surface of the pad oxide, to a wet dip. During this latter step, care must be taken that the STI oxide is removed such that the surface planarity of the STI is maintained even to the point where the surface of the now reduced STI oxide is in the plane of the surface of the substrate. This latter objective is difficult to obtain due to differences in etch rates. It is therefore not uncommon to find that there is a need to provide special methods or materials such that the STI oxide, most notably in the perimeter of the surface of the STI oxide where this oxide interfaces with the surrounding substrate, maintains good planarity. The invention provides such a method by providing an impurity implantation into the deposited layer of STI oxide prior to the etch of this STI oxide.
U.S. Pat No. 6,258,676 Bl (Lee et al.) shows a STI planarization process using a reverse mask, etch back and CMP
U.S. Pat. No. 6,242,322 B1 (Chen et al.) shows a STI planarization process using a reverse poly mask.
U.S. Pat. No. 6,194,285 B1 (Lin) shows a STI planarization process using a reverse mask.
U.S. Pat. No. 6,169,012 Bl (Chen et al.) shows a STI planarization process using a reverse mask and etch.
SUMMARY OF THE INVENTION
A principle objective of the invention is to prevent a recess or divot in the surface of a created fill of a Shallow Trench Isolation region.
In accordance with the objectives of the invention a new method is provided for the creation of STI regions. STI trenches are created in the surface of a substrate following conventional processing. A layer of STI oxide is deposited and, using an exposure mask that is a reverse mask of the mask that is used to create the STI pattern, impurity implants are performed into the surface of the deposited layer of STI oxide. In view of these processing conditions, the layer of STI oxide overlying the patterned layer of etch stop material is exposed to the impurity implants. This exposure alters the etch characteristics of the deposited layer of STI oxide where this STI oxide overlies the patterned layer of etch stop material. The etch rate of the impurity exposed STI oxide is increased by the impurity implantation, resulting in an etch overlying the patterned etch stop layer that proceeds considerably faster than the etch of the STI oxide that is deposited overlying the created STI trenches. Since, without an impurity implant, the deposited layer of STI oxide etches at a uniform rate, the etch will remove the SIT oxide from the STI trench, thus causing a recess in the surface of the STI oxide inside the STI trenches. With the significantly faster etch of the STI oxide where this oxide has been exposed to impurity implantation, the STI oxide removal can be equalized between the STI oxide that overlies the patterned etch stop layer and the oxide that has been deposited over the STI trenches.


REFERENCES:
patent: 5851899 (1998-12-01), Weigand
patent: 5943590 (1999-08-01), Wang et al.
patent: 6124183 (2000-09-01), Karlsson et al.
patent: 6169012 (2001-01-01), Chen et al.
patent: 6194285 (2001-02-01), Lin et al.
patent: 6207533 (2001-03-01), Gao
patent: 6242322 (2001-06-01), Chen et al.
patent: 6258676 (2001-07-01), Lee et al.

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