STI punch-through defects and stress reduction by high...

Details STI punch-through defects and stress reduction by high... STI punch-through defects and stress reduction by high...

1999-02-04

2001-10-30

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S632000

Reexamination Certificate

active

06309942

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to transistors formed on a semiconductor device, and more particularly to a method of reducing punch-through defects and stress experienced by transistors through a high temperature oxide reflow process.
BACKGROUND OF THE INVENTION
Isolating devices that are fabricated on a semiconductor substrate is a significant aspect of modern semiconductor chip manufacturing. This is especially true in very-large-scale integration (“VLSI”) and ultra-large-scale integration (“ULSI”) semiconductor chips because hundreds of thousands of devices are fabricated in a single semiconductor chip. If two transistors or other devices are fabricated too close to one another, they will not work because they will be electrically shorted together. In addition, incorrect isolation among transistors can cause current leakage and further escalate latch-up that can impair proper functioning of the circuits on the semiconductor chip either momentarily or permanently.
In metal-oxide-semiconductor (“MOS”) transistor fabrication, isolation is accomplished by forming isolation regions between neighboring active regions on the semiconductor chip. These isolation regions are formed by ion-doping a channel stop of polarity opposite to the source electrode and the drain electrode of the integrated circuit device, and by growing a thick oxide, commonly referred to as a field oxide. The channel stop and the thick oxide cause the threshold voltage in the isolation region to be much higher than those of the neighboring active devices.
One common approach in the semiconductor industry for forming isolation regions is by the localized oxidation of silicon (“LOCOS”) method. LOCOS uses a patterned silicon nitride (“Si
3
N
4
”) layer as an oxidation barrier mask and the silicon substrate is then selectively oxidized to form semi-planar isolation regions. The active devices are formed in the area defined by the silicon nitride layer. After oxidation, the silicon nitride layer is typically removed leaving a free area for the formation of the remaining circuit components.
An alternative to the LOCOS method of forming isolation regions is to use shallow trench isolation (“STI”). In this method, trenches are etched in the silicon substrate through microlithography techniques. The trenches are then filled using conventional deposition techniques with silicon dioxide, commonly some form of tetraethyl orthosilicate (“TEOS”). The silicon dioxide is then etched back or polished using chemical mechanical polishing (“CMP”) to form the field oxide isolation regions.
As the active regions and the isolation regions in semiconductor devices have become more dense, it has been observed that a very small amount of transistors (approximately 5 out of 128,000) exhibit massive amounts of transistor leakage in some semiconductor chips. The transistor leakage experienced was not gate modulated so regular punch-through leakage was not the source of the transistor leakage. SEM micrographs of semiconductor chips that exhibit this transistor leakage have shown that the source and drain of the failed transistors were shorted by a punch-through killer defect in the channel of the failed transistors. While the source of this defect is not well understood, some references suggest that these defects may be stress related. Therefore, a need has arisen for a method of manufacturing a semiconductor chip that solves the problems associated with this defect in the channel of the failed transistors due to stress experienced during manufacturing.
SUMMARY OF THE INVENTION
The present invention provides a method of manufacturing a semiconductor device that reduces the number of punch-through killer defects that occur in transistors as a result of stress experienced during the manufacturing process. In the invention, the semiconductor device being manufactured is annealed at a temperature in excess of 1150° C. The method of manufacturing semiconductor devices begins by depositing a capping layer on the surface of a silicon substrate. After the capping layer is deposited, a plurality of isolation trenches are etched through the capping layer into the silicon substrate. Each respective isolation trench is then filled with an oxide layer using conventional deposition techniques known in the art. Once the isolation trenches have been filled, the oxide layer and the capping layer are polished back using conventional polishing techniques known in the art, such as CMP. The resulting device is then annealed between the temperatures of about 1150° C. to about 1200° C.
Annealing the semiconductor device at temperatures in excess of about 1150° C. relieves the strain associated with the shrinkage of the oxide layer that is deposited to fill the trenches of the semiconductor device. Silicon dioxide's glass transition temperature is near 1000° C., and it can undergo stress relaxation by viscous flow at temperatures above its glass transition temperature. If the semiconductor device is annealed at a high enough temperature, such that the viscous flow stress relief is greater than the stress generated from the annealing, the punch-through killer defects in the active area of the semiconductor device may be greatly reduced.
The method of the invention reduces the punch-through killer defects by decreasing the stress experienced by the active regions of transistors located on the semiconductor device. The volume shrinkage of the isolation regions of the transistors fabricated on the semiconductor device during the post CMP high temperature densification process can generate more than 5% strain. This strain creates a large amount of Von Mises Stress in the active regions and punch-through killer defects may occur in the active areas as a result of this stress. In order to relieve this stress, a high temperature oxide reflow process is used as one of the steps after STI formation in the process of manufacturing the semiconductor device. According to the process of the invention, the annealing temperature is increased from about 1000° C. to about 1150° C.-1200° C.
These and other features and advantages of the invention will become apparent upon consideration of the following detailed description of the presently preferred embodiments of the invention, viewed in conjunction with the appended drawings.


REFERENCES:
patent: 4486266 (1984-12-01), Yamaguchi
patent: 5256550 (1993-10-01), Laderman et al.
patent: 5449953 (1995-09-01), Nathanson et al.
patent: 5712185 (1998-01-01), Tsai et al.
patent: 5726090 (1998-03-01), Jang et al.
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5731611 (1998-03-01), Hshieh et al.
patent: 5747377 (1998-05-01), Wu
patent: 6037247 (2000-03-01), Anand
patent: 6060387 (2000-05-01), Shepela et al.
patent: 6124189 (2000-09-01), Watanabe et al.
patent: 6147000 (2000-11-01), You et al.
patent: 6218289 (2001-04-01), Wu
“Mechanical Stress Induced MOSFET Punch-through and Process Optimization for Deep Submicron TEOS-O3 filled STI Device”, 1997 Symposium on VLSI Technology Digest of Technical Papers, K. Ishimaru, F. Matsuoka, M. Takahashi, M. Nishigohri., Y. Okayama, Y. Unno, M. Yabuki, K. Umezaza, N. Tsuchiya, O. Fujii and Y. M. Kinugawa, 2 Pages.
“Stress Minimization in Deep Sub-Micron Full CMOS Devices by Using an Optimized Combination of the Trench Filling CVD Oxides”, M. H. Park, S. H. Hong, S. J. Hong, T. Park, S. Song, J. H. Park, H. S. Kim, Y. G. Shin, H. K. Kang and M. Y. Lee, 4 Pages.
“In-situ Measurement of Viscous Flow of Thermal Silicon Dioxide Thin Films at High Temperature”, Chia-Liang Yu, Paul A. Flinn and John C. Bravman, 6 Pages.

Affiliated with

Also associated with

Rating

STI punch-through defects and stress reduction by high... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with STI punch-through defects and stress reduction by high..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and STI punch-through defects and stress reduction by high... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2613534