Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
2001-01-25
2004-01-06
Baumeister, Bradley W. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S586000, C257S592000, C257S616000
Reexamination Certificate
active
06674102
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to heterojunction bipolar transistors, and more particularly to a method of fabricating a SiGe heterojunction bipolar transistor wherein the base resistance is improved by employing an etching process that controls facet growth at the edges of the SiGe layer. Specifically, the present invention controls the facet growth by providing a recessed area in isolation regions that are present in the structure.
BACKGROUND OF THE INVENTION
Significant growth in both high-frequency wired and wireless markets has introduced new opportunities where compound semiconductors such as SiGe have unique advantages over bulk complementary metal oxide semiconductor (CMOS) technology. With the rapid advancement of epitaxial-layer pseudomorphic SiGe deposition processes, epitaxial-base SiGe heterojunction bipolar transistors have been integrated with mainstream advanced CMOS development for wide market acceptance, providing the advantages of SiGe technology for analog and RF circuitry while maintaining the full utilization of the advanced CMOS technology base for digital logic circuitry.
A typical prior art SiGe heterojunction bipolar transistor is shown, for example, in FIG.
1
. Specifically, the SiGe heterojunction bipolar transistor shown in
FIG. 1
comprises semiconductor substrate
10
of a first conductivity type having sub-collector
14
and collector
16
formed therein. Isolation regions
12
, which are also present in the substrate, define the outer boundaries of the bipolar transistor. The bipolar transistor of
FIG. 1
further includes SiGe layer
20
formed on a surface of substrate
10
as well as isolation regions
12
. The SiGe layer includes polycrystalline Si regions
24
that are formed over the isolation regions and SiGe base region
22
that is formed over the collector and sub-collector regions. The prior art bipolar transistor also includes patterned insulator layer
26
formed on the base region and emitter
28
formed on the patterned insulator layer as well as a surface of SiGe base region
22
.
A major problem with prior art SiGe heterojunction bipolar transistors of the type illustrated in
FIG. 1
is that during the deposition of the SiGe layer, facet regions (labeled as
30
in
FIG. 1
) grow at the edges of the SiGe layer between the polycrystalline Si region and the SiGe base region. As shown, the facets form in regions which encroach upon the corner formed between the upper surfaces of substrate
10
and the isolation regions of the structure. The growth of facets near the this corner leads to increased parasitic current leakage as well as shorts which are caused by the presence of excessive dislocations in the structure. Moreover, the presence of facets in a bipolar transistor increases the base resistance of the structure.
In view of the above mentioned problems with prior art heterojunction bipolar transistors, there is still a continued need for developing a new and improved method which is capable of fabricating a heterojunction bipolar transistor in which facet growth is controlled such that the structure will have reduced dislocations and base resistance as well as diminished parasitic leakage.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a SiGe heterojunction bipolar transistor wherein the SiGe base resistance is reduced.
Another object of the present invention is to provide a method of fabricating a SiGe heterojunction bipolar transistor in which facet growth is controlled such that facets do not form at the corners that exist between the upper surfaces of the substrate and the isolation regions.
A further object of the present invention is to provide a method of fabricating a SiGe heterojunction bipolar transistor in which diminished parasitic current leakage is achieved.
These and other objects and advantages are achieved in the present invention by forming a pull-down isolation region. The pull-down isolation region is formed in the present invention by recessing a portion of the isolation region prior to forming the SiGe layer on the structure. During SiGe deposition, the facets do not encroach upon the corner that exists between upper surfaces of the substrate and the pull-down isolation region.
Specifically, the method of the present invention comprises the steps of:
(a) providing a semiconductor substrate having isolation regions formed therein, said semiconductor substrate having an upper surface;
(b) recessing a portion of the isolation regions below the upper surface of said semiconductor substrate so as to provide a recessed isolation surface; and
(c) forming a SiGe layer on the upper surface of the semiconductor substrate as well as the recessed isolation surface, wherein said recessing controls facet growth at edges of the SiGe layer thereby reducing dislocations therein.
After conducting steps (a)-(c) above, conventional processing steps can be employed to form the emitter region of the bipolar transistor.
In one embodiment of the present invention, a dielectric layer such as a nitride is formed on portions of the isolation regions which are not recessed prior to formation of the SiGe layer. In addition to being formed on the non-recessed surfaces of the isolation regions, it is contemplated in the present invention to use the dielectric as an etch mask in making the pull-down isolation regions. When this embodiment is employed, a patterned dielectric is formed on portions of the isolation regions prior to recessing, and an etching process that is highly selective in removing the isolation fill material as compared to the dielectric may be employed.
Another aspect of the present invention relates to a SiGe heterojunction bipolar transistor which includes pull-down isolation regions formed therein. Specifically, the inventive SiGe bipolar transistor comprises:
a semiconductor substrate having a collector and sub-collector formed therein, wherein said collector is formed between isolation regions that are also present in the substrate, each of said isolation regions having a recessed surface and a non-recessed surface;
a SiGe layer formed on said substrate as well as said recessed and non-recessed surfaces of each isolation region, said SiGe layer including polycrystalline Si regions and a SiGe base region;
a patterned insulator layer formed on said SiGe base region, said patterned insulator layer having an opening therein; and
an emitter formed on said patterned insulator layer and in contact with said SiGe base region through said opening.
In one embodiment of the present invention, the inventive SiGe heterojunction bipolar transistor includes a patterned dielectric material which is present on the non-recessed surface of the isolation regions.
REFERENCES:
patent: 4861393 (1989-08-01), Bean et al.
patent: 4887145 (1989-12-01), Washio et al.
patent: 5120394 (1992-06-01), Mukai
patent: 5506427 (1996-04-01), Imai
patent: 5587327 (1996-12-01), Konig et al.
patent: 5861640 (1999-01-01), Gomi
patent: 5955745 (1999-09-01), Yamazaki
patent: 6303419 (2001-10-01), Chang et al.
patent: 1984000152265 (1986-02-01), None
patent: 1985000072889 (1986-10-01), None
patent: 1922000238930 (1994-03-01), None
patent: 2000-294564 (2000-10-01), None
Coolbaugh Douglas Duane
Dupuis Mark D.
Gallagher Matthew D.
Geiss Peter J.
Philips Brett A.
Baumeister Bradley W.
International Business Machines - Corporation
Sabo William D.
Scully Scott Murphy & Presser
LandOfFree
Sti pull-down to control SiGe facet growth does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Sti pull-down to control SiGe facet growth, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sti pull-down to control SiGe facet growth will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3210337