STI formation for vertical and planar transistors

Details STI formation for vertical and planar transistors STI formation for vertical and planar transistors

2005-05-17

2005-05-17

Wilson, Christian (Department: 2824)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S717000, C438S735000, C438S736000

Reexamination Certificate

active

06893938

ABSTRACT:
A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.

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