Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
2005-05-17
2005-05-17
Zarneke, David A. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S106000, C438S108000, C438S110000, C438S112000, C438S121000, C438S124000, C438S778000, C438S780000, C438S781000
Reexamination Certificate
active
06893904
ABSTRACT:
A method for forming packaged substrates, including flip-chip dice individually or in a multi-die wafer. The method includes using a stereolithographic process to form a protective dielectric polymeric sealing structure on at least the active surface of the substrate. In addition, the invention encompasses forming a similar layer on a second substrate to be joined to the first substrate. Contact pads of the second substrate are exposed through the layer thereon to facilitate joining of the two substrates. Semiconductor devices formed by the method are also disclosed.
REFERENCES:
patent: 4273859 (1981-06-01), Mones et al.
patent: 5173220 (1992-12-01), Reiff et al.
patent: 5264061 (1993-11-01), Juskey et al.
patent: 5484314 (1996-01-01), Farnworth
patent: 5705117 (1998-01-01), O'Connor et al.
patent: 5773198 (1998-06-01), Swirbel et al.
patent: 5839722 (1998-11-01), Berlin et al.
patent: 6013419 (2000-01-01), Tani et al.
patent: 6177360 (2001-01-01), Carter et al.
patent: 6197397 (2001-03-01), Sher et al.
patent: 6200646 (2001-03-01), Neckers et al.
patent: 6203885 (2001-03-01), Sher et al.
patent: 6251488 (2001-06-01), Miller et al.
patent: 6259962 (2001-07-01), Gothait
patent: 6268584 (2001-07-01), Keicher et al.
patent: 6326698 (2001-12-01), Akram
patent: 6337122 (2002-01-01), Grigg et al.
patent: 6391251 (2002-05-01), Keicher et al.
patent: 6432752 (2002-08-01), Farnworth
patent: 6461881 (2002-10-01), Farnworth et al.
patent: 6482576 (2002-11-01), Farnworth et al.
patent: 6489007 (2002-12-01), Grigg et al.
patent: 6506671 (2003-01-01), Grigg
patent: 6514798 (2003-02-01), Farnworth
patent: 6525408 (2003-02-01), Akram et al.
patent: 6544821 (2003-04-01), Akram
patent: 6544902 (2003-04-01), Farnworth
patent: 6548897 (2003-04-01), Grigg
patent: 6549821 (2003-04-01), Farnworth et al.
patent: 6562278 (2003-05-01), Farnworth et al.
patent: 6569753 (2003-05-01), Akram et al.
patent: 5593171 (2003-07-01), Farnworth
patent: 6585927 (2003-07-01), Grigg et al.
patent: 6630365 (2003-10-01), Farnworth et al.
patent: 6635333 (2003-10-01), Grigg et al.
patent: 6649444 (2003-11-01), Earnworth et al.
patent: 20020043711 (2002-04-01), Akram et al.
patent: 20020066966 (2002-06-01), Farnworth
patent: 20020098623 (2002-07-01), Akram
patent: 20020105074 (2002-08-01), Akram
patent: 20020171177 (2002-11-01), Kritchman et al.
patent: 20020182782 (2002-12-01), Farnworth
patent: 20030003180 (2003-01-01), Farnworth et al.
patent: 20030003380 (2003-01-01), Farnworth et al.
patent: 20030003405 (2003-01-01), Farnworth et al.
patent: 20030022462 (2003-01-01), Farnworth et al.
patent: 20030043360 (2003-03-01), Farnworth
patent: 20030068584 (2003-04-01), Farnworth et al.
patent: 20030072926 (2003-04-01), Grigg et al.
patent: 20030077418 (2003-04-01), Grigg et al.
patent: 20030093173 (2003-05-01), Farnwoth et al.
patent: 20030098499 (2003-05-01), Akram et al.
patent: 20030102566 (2003-06-01), Farnworth
patent: 20030129787 (2003-07-01), Farnworth
patent: 20030139030 (2003-07-01), Grigg
patent: 20030151167 (2003-08-01), Kritchman et al.
patent: 20030170921 (2003-09-01), Akram
patent: 20030173665 (2003-09-01), Grigg
patent: 20030176016 (2003-09-01), Grigg
patent: 20030201531 (2003-10-01), Farnworth et al.
patent: 20030203158 (2003-10-01), Farnworth et al.
patent: 20030203612 (2003-10-01), Akram et al.
patent: 0006052 (1979-12-01), None
patent: 9-17783 (1997-01-01), None
patent: 9-36115 (1997-02-01), None
patent: 9-64537 (1997-03-01), None
Miller et al., “Maskless Mesoscale Materials Depositions”, Deposition Technology, Sep. 2001, pp. 20-22.
Miller, “New Laser-Directed Deposition Technology”, Microelectronic Fabrication, Aug. 2001, pp. 16.
Webpage, Object Prototyping the Future, “Object FullCure700 Series”, 1 page.
Webpage, Object Prototyping the Future, “How it Works”, 2 pages.
U.S. Appl. No. 09/589,841, filed Jun. 8, 2000 entitled “Stereolithographic Methods for Forming a Protective Layer on a Semiconductor Device Substrate and Substrates Including Protective Layers So Formed”, inventor Farnworth et al.
U.S. Appl. No. 09/590,527, filed Jun. 8, 2000, entitled “Structures for Stabalizing Semiconductor Devices Relative to Test Substrates and Methods for Fabricating the Stabalizers” , inventor Salman Akram.
U.S. Appl. No. 09/590,621, filed Jun 8, 2000, entitled “Stereolithographic Method and Apparatus for Fabricating Stablizers for Flip-Chip Type Semiconductor Devices and Resulting Structures”, inventor Akram et al.
U.S. Appl. No. 09/651,930, filed Aug. 31, 2000, entitled “Semiconductor Device Including Leads in Communication with Contact Pads Thereof and a Stereolithograhically Fabricated Package Substantially Encapsulating the Leads and Methods for Fabricating the Same”, inventor Salman Akram.
U.S. Appl. No. 10/201,208, filed Jul 22, 2002, entitled “Thick Solder Mask for Confining Encapsulant Material Over Selected Locations of a Substrate, Assemblies Including the Solder Mask, and Methods”, inventor Grigg et al.
U.S. Appl. No. 10/370,755, filed Feb. 20, 2003, entitled “Chip Scale Packages Structures and Method of Forming Conductive Bumps Thereon”, inventor Warren M. Farnworth.
U.S. Appl. No. 10/455,091, filed Jun. 5, 2003, entitled “Methods for Sterolithographic Processing of Components and Assemblies”, inventor Warren M. Farnworth.
U.S. Appl. No. 10/608,749, filed Jun. 26, 2003, entitled “Methods for Labeling Semiconductor Device Components”, inventor Grigg et al.
U.S. Appl. No. 10/619,918, filed Jul. 15, 2003, entitled “Stereolithographic Methods for Fabricating Hermetic Semiconductor Device Packages and Semiconductor Devices Including Stereolithographically Fabricated Hermetic Packages”, inventor Warren M. Farnwoth.
U.S. Appl. No. 10/672,098, filed Sep. 26, 2003, entitled “Apparatus and Methods for Use in Stereolithographic Processing of Components and Assemblies”, inventor Warren M. Farnworth.
U.S. Appl. No. 10/688,354, filed Oct. 17, 2003, entitled “Thick Solder Mask for Confining Encapsulant Material Over Selected Locations of a Substrate and Assemblies Including the Soldier Mask”, inventor Grigg et al.
U.S. Appl. No. 10/690,417, filed Oct. 20, 2003, entitled “Methods of Coasting and Singulating Wafers and Chip-Scale Packages Formed Therefrom”, inventor Farnworth et al.
Micro)n Technology, Inc.
TraskBritt
Zarneke David A.
LandOfFree
Stereolithographic methods of fabricating semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stereolithographic methods of fabricating semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stereolithographic methods of fabricating semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3373846