Optics: measuring and testing – By alignment in lateral direction – With registration indicia
Reexamination Certificate
1999-08-26
2001-07-24
Font, Frank G. (Department: 2877)
Optics: measuring and testing
By alignment in lateral direction
With registration indicia
C356S365000, C356S023000, C356S237200
Reexamination Certificate
active
06266144
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to stepper exposure systems and more particularly to correction methods and apparatus therefor.
2. Description of Related Art
U.S. Pat. No. 4,823,012 of Kosugi for “Step and Repeat Exposure Apparatus Having Improved System for Aligning” describes alignment marks provided in association with neighboring fields on a wafer which are to be exposed to a reticle pattern in sequence.
U.S. Pat. No. 4,982,227 of Suzuki for “Photolithographic Exposure Apparatus with Multiple Alignment Modes” shows a method for alignment using multiple alignment modes by adapting an alignment method by a sample alignment prior to the exposure operation. The alignment modes examine multiple sized fields.
U.S. Pat. Re. 33,836 of Resor, et al. for “Apparatus and Method for Making Large Area Electronic Devices, Such as Flat Panel Displays and the Like, Using Correlated, Aligned Dual Optical Systems” shows an alignment method for substrates (displays not chips) that includes a means for aligning images.
U.S. Pat. No. 5,444,538 of Pellegrini for “System and Method for Optimizing the Grid and Intrafield Registration of Wafer Patterns” describes measurement of overlay misregistration and a method for optimizing the (grid) interfield and intrafield registration of dies.
U.S. Pat. No. 5,655,110 of Krivokapic et al. for “Method for Setting and Adjusting Process Parameters to Maintain Critical Dimensions across each Die of Mass-Produced Semiconductor Wafers” teaches a method for adjusting alignment parameters to optimize the photo process.
U.S. Pat. No. 5,633,505 of Chung et al., commonly assigned, for “Semiconductor Wafer Incorporating Marks for Inspecting First Layer Overlay Shift in Global Alignment Process” relates to overlay inspection.
See the Morita et al. reference “Impacts of Reticle and Wafer Elasticity Control on Overall Alignment Management Strategy”, SPIE Vol. 3334, pp 510-518, 0277-786X/98.
U.S. Pat. No. 5,841,144 of Cresswell for “Overlay Target and Measurement Procedure to Enable Self-Correction for Wafer-Induced Tool-Induced Shift by Imaging Sensor Means” discusses in the abstract “test structure elements . . . with one component of each spaced at progressively greater distances from an arbitrary baseline, such that a zero overlay element may be identified by the alternative imaging senor means”.
U.S. Pat. No. 5,879,866 of Starikov et al. for “Image Recording Process with Improved Image Tolerances Using Embedded AR Coatings” discusses self-correction of overlay using antireflective materials.
In the current state of the art, the optical stepper exposure sequence depends only on the level at which the sensor can work on the dies to be exposed or can not work on the dies because of distortion problems related to expansion generated by heating of elements of the system which leads to misalignment. Thus there a is need to solve this distortion problem.
SUMMARY OF THE INVENTION
Heretofore, exposure systems have not considered intra-field distortion insofar as it relates to the exposure sequence. For that reason, with the current state of the art, the impact of the sequence of exposure as related to correction analysis of misalignment of overlay can not be optimized, especially on an intra-field basis. In the past, no algorithm has been provided for analyzing intra-field errors caused by the exposure sequence employed by the exposure system.
A principal purpose of this invention is to achieve maximum efficiency during exposure of a wafer by a stepper through a reticle by reducing the impact of thermal distortion problems during exposure.
Features of this invention include as follows:
1. The exposure sequence from the center of the wafer through the same radius array sequence provides better control of the degree of overlay misregistration.
2. Measurement of the degree of overlay misregistration should pick dies on the edge of a wafer which can represent a maximum degree of distortion. Through this exposure sequence, optimization of the overlay registration can be achieved by minimizing the degree of misregistration.
3. According to this exposure sequence, steppers and scanners facilitate the design of an algorithm for calculating the intrafield reduction ratio to minimize heat expansion.
This invention provides an exposure sequence which permits overlay measurement with a better model for analyzing wafer overlay correction.
The resultant heat expansion correction algorithm employs this exposure sequence to minimize intrafield error.
A method and system are provided for determining the degree of over-lay misregistration when exposing a semiconductor wafer having a center and a periphery as follows. Expose the wafer with a scan in a sequence from the center of the wafer to the periphery. Select dies on the periphery of a wafer for measurement which represent a maximum degree of distortion, and employ a correction algorithm for calculating an intrafield reduction ratio to minimize heat expansion.
REFERENCES:
patent: Re. 33836 (1992-03-01), Resor, III et al.
patent: 4347011 (1982-08-01), Levy et al.
patent: 4823012 (1989-04-01), Kosugi
patent: 4982227 (1991-01-01), Suzuki
patent: 5438413 (1995-08-01), Mazor et al.
patent: 5444538 (1995-08-01), Pellegrini
patent: 5633505 (1997-05-01), Chung et al.
patent: 5655110 (1997-08-01), Krivokapic et al.
patent: 5841144 (1998-11-01), Cresswell
patent: 5879866 (1999-03-01), Starikov et al.
Morita et al., “Impacts of Reticle and Wafer Elasticity Control on Overall Alignment Management Strategy”, SPIE vol. 3334, pp. 510-518, 0277-786x/98.
Ackerman Stephen B.
Font Frank G.
Jones II Graham S.
Punnoose Roy M.
Saile George O.
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