Communications: electrical – Digital comparator systems
Patent
1979-04-03
1982-01-05
Boudreau, Leo H.
Communications: electrical
Digital comparator systems
3401463CA, 364200, 364515, G06K 1300, G06K 900
Patent
active
043096913
ABSTRACT:
Architecture for step-oriented pipeline data processing is disclosed utilizing a plurality of cascaded modules, each module including a programmable general purpose processor and a read/write random access memory. The memory of each module, shared with the next module in cascade serves as an output memory for the processor and the input memory for the next processor. An additional memory is provided to serve as the input memory of the first module, and each module is provided with a memory, which may be a read-out memory, to store a program for the processor. Each module is further provided with a logic network for resolving a potential memory sharing conflict by awarding priority to the processor of the module.
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Boudreau Leo H.
California Institute of Technology
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