Steered frequency phase locked loop

Details Steered frequency phase locked loop Steered frequency phase locked loop

1997-09-30

2000-02-29

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331 2, 331 16, 331 17, 331 23, 331 25, 327156, 375376, 455260, 329302, 329307, 329325, 329360, H03L 707, H03L 7087, H03D 100, H03D 300

Patent

active

060314281

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

This invention relates to improvements in Phase Locked Loops (PLL) and relates particularly to a Steered Frequency Phase Locked Loop (SFPLL). The SFPLL is a system that exhibits PLL like behaviour but the range of frequencies to which it can lock is controlled. This invention has applications in many diverse areas of electronics, for example: timing recovery in base-band digital transmission, demodulation in continuous wave (CW) modulation systems, and filtering of electrical signals.


BACKGROUND TO THE INVENTION

Most conventional PLLs have problems with false locking onto unwanted input signals, or unwanted spectral components of the input signal. The SFPLL avoids this false locking problem as the range of frequencies to which the SFPLL can lock can be confined to an arbitrarily small region around the desired input signal (providing of course the frequency of the input signal is known with sufficient accuracy). The SFPLL typically will not false lock providing there are no unwanted input signals, or unwanted spectral components of the input signal, in the range of frequencies to which the SFPLL can lock.
Exceptionally accurate positioning and confinement of the locking range of the SFPLL can be achieved by use of precise frequency detectors and an accurate reference frequency .omega.'.sub.r.


SUMMARY OF THE INVENTION

According to one aspect of the present invention there is provided a steered frequency phase locked loop (SFPLL) comprising: adapted to lock the phase of the output signal to that of the input signal; and, input signal providing a reference frequency, wherein the frequency loop uses the reference frequency to steer the phase loop and effectively confines the range of frequencies to which the phase loop can lock close to the reference frequency.
Preferably said phase loop comprises a phase detector, and a voltage controlled oscillator operatively coupled to an output of said phase detector, an output of said voltage controlled oscillator being connected to an input of said phase detector to complete the phase loop.
Preferably said frequency loop comprises a frequency detector, and means for summing respective output signals of said phase detector and frequency detector and supplying the sum to said voltage controlled oscillator, the output of said voltage controlled oscillator being connected to an input of said frequency detector to complete the frequency loop.
Preferably said phase loop and frequency loop further comprise first and second gain components respectively. Preferably said SFPLL further comprises a first signal filtering means operatively connected between said summing means and said voltage controlled oscillator.
Typically said phase loop has a second signal filtering means operatively connected to the output of said phase detector for filtering the output signal from said phase detector. Typically said frequency loop has a third signal filtering means operatively connected to an output of said frequency detector for filtering the output signal of said frequency detector.
Advantageously the SFPLL can be applied to demodulation in continuous wave (CW) modulation systems (both AM and FM), or to timing recovery from a data stream.
Like conventional PLLs the SFPLL takes an input signal which it is required to phase lock to. In addition to this input signal, the SFPLL has an accurate reference frequency input of frequency .omega.'.sub.r. The reference frequency .omega.'.sub.r is chosen to be close to (though not necessarily the same as) the frequency of the input signal which the SFPLL is required to phase lock to. Three key advantages of the SFPLL are: the output frequency is .omega.'.sub.r (or is close to .omega.'.sub.r) when no input signal is present, the range of frequencies to which the SFPLL can lock is confined to a region around .omega.'.sub.4, and the phase and frequency instabilities of the VCO are reduced.


BRIEF DESCRIPTION OF THE DRAWINGS

In order to facilitate a more comprehensive understanding of the nature of the invention a preferred em

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