Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
1999-03-18
2001-01-30
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S278000
Reexamination Certificate
active
06181183
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logic circuit wherein delay stages having steep edges are realized with a relatively minor component outlay.
2. Description of the Prior Art
In logic circuits, delayed edges are frequently required in order to control sequential operations. However, long delays also simultaneously manifest a slowing-down of the edges and/or a reduction in the edge steepness. Such delays may be realized by a large number of simple circuits; for example, by invertor cascades. A series circuit formed by an RC element and/or an integrator and a downstream Schmitt trigger, for example, constitutes one measure for overcoming this problem. The disadvantage of this is that such a circuit is relatively complicated.
SUMMARY OF THE INVENTION
The present invention is based on the object of specifying a delay stage with steep edges which requires as little circuitry as possible.
Accordingly, in an embodiment of the present invention, a circuit with a delay stage is provided which includes: a first inverter having both a p-channel MOS transistor and an n-channel MOS transistor; a second inverter having both a p-channel MOS transistor and a n-channel MOS transistor, wherein the second inverter is connected in series with the first inverter such that an input of the first inverter corresponds to an input of the delay stage and an output of the second inverter corresponds to an output of the delay stage; a p-channel MOS transistor connected as a capacitor between a gate of the p-channel MOS transistor of the second inverter and the output of the delay stage; and an n-channel MOS transistor connected as a capacitor between the output of the delay stage and a gate of the n-channel MOS transistor of the second inverter.
In an embodiment, both the p-channel MOS transistor and the n-channel MOS transistor of the first inverter have a significantly higher impedance than both the p-channel MOS transistor and the n-channel MOS transistor of the second inverter in an ON state.
Additional features and advantages of the present invention are described in, and will be apparent from, the Detailed Description of the Preferred Embodiments and the Description of the Drawings.
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Bollu Michael
Schmitt-Landsiedel Doris
Thewes Roland
VON Basse Paul-Werner
Lam Tuan T.
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
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