Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2000-02-24
2001-08-07
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S189011
Reexamination Certificate
active
06272033
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems using cache memory that incorporates at least one status bit associated with each data word within the cache memory.
2. Description of the Prior Art
It is known to provide cache memories, such as that illustrated in
FIG. 1
of the accompanying drawings, that include store
2
containing address TAGs for lines of data in a cache RAM memory
4
. The cache RAM memory
4
is composed of a plurality of cache lines
6
, each cache line
6
storing four data words. A plurality of valid and dirty bits
8
are associated with each cache line
6
. Common types of status bits
8
are a valid bit
10
and a dirty bit
12
. The valid bit
10
indicates whether that cache line is storing valid data, e.g. at startup each cache line
6
must be marked as storing invalid data. The dirty bit
12
indicates in the context of a write back cache architecture that at least one data word with that cache line
6
has been changed since it was read from the main memory and accordingly needs writing back to the main memory when that cache line
6
is flushed from or replaced within the cache. It will be seen that as a compromise between circuit area and the degree of fine control that can be achieved with the status bits
8
, each cache line
6
has one valid bit
10
associated with it and one dirty bit
12
associated with it (this is the arrangement used in the majority of cache implementations). Thus, the four data words within a cache line
6
share these status bits
8
.
In certain operational situations it is desirable to make global changes to the status bits
8
of all of the cache lines
6
of a cache system. As an example, upon system startup, following an MMU change or following a context switch, it is often necessary to flush the entire contents of the cache by marking all of the valid bits
10
of each cache line
6
as invalid. One way of doing this is to sequentially access each of the valid bits
10
and write it invalid. In a cache system that may contain thousands of cache lines
6
, this operation can take thousands of processing cycles and significantly impact system performance. An alternative to sequentially and individually altering each of the status bits
8
is to apply a global change through special purpose hardware that is able to change the status bits in parallel. Whilst this can provide fast operation, it has the disadvantage of consuming circuit area for this special purpose hardware and typically requires to be custom designed for each implementation of a more generic system design.
SUMMARY OF THE INVENTION
The present invention is concerned with providing mechanisms for changing status bits at high speed, possibly as fast as one processing cycle, without having to provide custom hardware for the parallel access of all of the status bits.
Viewed from one aspect the present invention provides apparatus for data processing, said apparatus comprising:
(i) a memory operable to store a plurality of data words, each data word being associated with at least one status bit giving information regarding a status of said data word;
(ii) a status bit store operable to store said status bits within a hierarchical relationship such that a combined status relating to a plurality of first level status bits at a first level within said hierarchical relationship is indicated by a second level status bit at a second level with in said hierarchical relationship, said second level being higher in said hierarchical relationship than said first level; and
(iii) status querying logic operative to determine a status of a data word within said memory by examining status bits within said status bit store starting at a top level within said hierarchical relationship and working down through said hierarchical relationship until a status bit is reached that indicates said status of said data word independently of any status bits lower in said hierarchical relationship.
The invention provides status bits arranged in a hierarchical relationship (having at least two levels) such that global or large-scale changes to the status of a plurality of data words within the memory may be made by changing relatively few status bits at the top or towards the top of the hierarchical relationship without having to individually change every status bit related to each data word for which the status is changing. In this way, the time taken to make global or large-scale changes to the status bits can be drastically reduced without the need to provide custom hardware for making large-scale change s in parallel to all of the status bits. It will be appreciated that many data words may share status bits. In some embodiments the hierarchy may be of valid bits and the data words to which these refer include, TAG values, data words, dirty bits and other status bits.
The status bits could represent a variety of different properties of the data words related to them. However, the invention is particularly suited to embodiments in which the status bits are valid bits indicative of validity of data words stored within the memory.
Valid bits are often subject to global or large-scale changes and so the invention is particularly useful in allowing these to be changed more rapidly and with reduced hardware cost.
It will be appreciated that at the lowest level within the hierarchical relationship an individual status bit could be provided for each data word. Thus, if the memory is a cache memory and a cache line stores four data words, then it would be possible to associate four separate valid bits with that cache line to indicate the validity of each individual data word. However, in preferred embodiments of the invention a lowest level status bit relates to a plurality of data words. This provides a satisfactory compromise between the granularity of fine control that can be achieved and the hardware resources required to provide the status bits.
More particularly, it is highly convenient to associate a lowest level status bit with all the data words within a cache row of the cache memory. In some embodiments a cache row may be considered to include its associated TAG values and dirty bits.
This arrangement has been found to work efficiently since cache accesses to and from the main memory typically take place on a cache-row-by-cache-row basis such that status information below the level of a cache row is rarely necessary due to the temporal and spatial locality that is in practice associated with most memory accesses.
The present invention suits itself to embodiments in which the status bits store includes a RAM memory storing status bit words formed of a plurality of status bits. The hierarchical relationship between these status bits and the status querying logic are such that the status bits towards the lower levels within the hierarchical relationship can be stored within RAM memory without significantly impacting performance and thereby gain the storage density advantages of RAM memory compared to custom latches or registers.
Storing the status bits within RAM memory allows them to be conveniently manipulated as status bit words that are accessed from the RAM memory.
In manipulating status bit words a typical operation will be a read-modify-write operation that is readily supported by existing data processing structures within many systems. Separate read and write operations may also be needed and in some RAM memories only read and write operations will be supported.
In contrast to the use of high-density RAM memory at the lowest levels within the status bits store, in preferred embodiments at least the highest level within the hierarchical relationship uses register bit circuits (D-Type) to store the status bits. Latch circuits can be very rapidly accessed and altered in response to predefined inputs or states, such as startup, MMU changes, context switches, etc., and accordingly provide rapid global or large-scale status changes with relatively litt
ARM Limited
Le Vu A.
Nixon & Vanderhye P.C.
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