Status bit controlled HDLC accelerator

Details Status bit controlled HDLC accelerator Status bit controlled HDLC accelerator

1994-12-28

1997-06-10

Hsu, Alpus H.

Multiplex communications

Communication techniques for information carried in plural...

Adaptive

370474, 39520017, 371 377, H04T 306

Patent

active

056383703

ABSTRACT:
A status bit controlled HDLC accelerator comprises a fully programmable CRC generation circuit, a partial data packet formatting/unformatting capability and a dual-mode register set. The HDLC accelerator includes a set of registers that can be written to and read from directly via a bus interface circuit. Moreover, these registers may be written to and read from at any time so that the state of the HDLC accelerator during a formatting or unformatting operation may be stored in mid-operation. The HDLC accelerator further includes a CRC generation circuit that can perform various checkword generation functions in response to a programmable CRC generator polynomial. In addition, programmable counters within the HDLC accelerator allow partial data packets to be processed which thereby enables formatting and unformatting data packets of all valid bit enumerations.

REFERENCES:
patent: 4979169 (1990-12-01), Almond et al.
patent: 5226173 (1993-07-01), Sasaki et al.
patent: 5307355 (1994-04-01), Lauck et al.
patent: 5361374 (1994-11-01), Sasaki et al.

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