Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-05-20
2001-07-03
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06255841
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuit (IC) testing and, more specifically, to a system and method for testing integrated circuits that involves statistical analysis.
BACKGROUND OF THE INVENTION
Static-current and circuit-level leakage tests are widely used to detect IC defects. However, these methods typically employ customer-defined or system level leakage limit requirements that are frequently too lenient and therefore incapable of removing devices that significantly stray from the desired population “outliers.” Historically, these device outliers have been proven to exhibit relatively poor early life performance. This weakness has been somewhat overcome through the use of statistically-based, production-level leakage limits to remove device outliers from production shipments. However, the quality and cost effectiveness of this method is limited by process-dependent, intrinsic transistor leakage variability.
Historically, many improvements in device deliverable quality and reliability have been attained through the use of statistically-based leakage limits (SBLL) as a means of removing leakage outliers from production shipments. These techniques are based on the theory that intrinsically good circuits exhibit a gaussian-like distribution of leakage current measurements. Conversely, devices containing point defects exhibit abnormally high leakage values relative to the parent population.
SBLL techniques employ descriptive statistics from a normal distribution of leakage current measurements to calculate ±3 sigma test limits that encompass 99.7% of the parent population. Devices that fall outside the SBLL include those that have been degraded by point defects. Aging experiments have consistently shown that this subset of leakage outliers yields significantly higher early life failure rates than the parent population. As a result, circuit designs tested using SBLL methods typically have higher levels of quality and reliability than products screened against customer-defined or system level requirement leakage limits.
Although SBLL techniques can significantly improve quality, the most significant detractor to their widespread use is the potential for high manufacturing costs resulting from excessive yield loss. This problem is most evident when the wafer fabrication process drifts near its allowable operating extremes causing the intrinsic semiconductor and circuit-level leakage characteristics to shift significantly. When this occurs, manufacturing yields become suppressed by a magnitude that is proportional to the shift in the leakage distribution. This yield suppression occurs because the previously defined SBLL become invalid, since the mean and sigma values from which they were derived no longer apply. Issues centered on the cost, quantity, and shipping requirements of said product typically result in burn-in evaluation experiments of the marginal leakage failures. These evaluations typically support the release of affected product to meet immediate customer demand, thereby reducing organizational support of SBLL test methods and ultimately resulting in poorer outgoing quality.
Another less apparent weakness of conventional SBLL methods stems from normal time-based process variations. These variations are reflected in circuit level leakage measurements even though their impact may seem relatively superficial. However, during a process capability study phase in which a cross-section sampling of production lots are evaluated, even minor time-based process variations can act to distort the calculated standard deviation of circuit level leakage from which SBLLs are derived. Excessively wide SBLL may result, which reduce defect-screening effectiveness by allowing some leakage outliers near the tails of the parent population to be shipped to the customer.
Accordingly, what is needed in the art is an effective method of screening leakage outliers from the intrinsic parent population with minimal negative impact on manufacturing costs and customer service.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a system for, and method of, testing a sample IC and a test apparatus incorporating the system or the method. The sample IC includes symmetrical circuits having corresponding intrinsic leakages that depend upon a process employed to manufacture the sample IC. In one embodiment, the system includes: (1) data storage circuitry that contains data derived statistically from exemplary ICs manufactured according to the process and determined to be acceptable and (2) test circuitry, associated with the data storage circuitry, that measures the corresponding intrinsic leakages to determine whether the sample IC is acceptable.
The present invention is the first to recognize that, since leakages in ICs are process-dependent, they should not unduly influence quality control. The present invention tempers the influence of leakage variations by statistically deriving data regarding acceptable ICs that have been manufactured according to a given process and applying the statistically derived data to leakages measured in a sample IC to determine whether the sample IC is acceptable. For purposes of the present invention, “symmetrical” is defined as substantially symmetrical, rather than precisely symmetrical. The circuits must be symmetrical enough such that leakages substantially offset one another.
In one embodiment of the present invention, the test circuitry determines whether the corresponding intrinsic leakages fall within an acceptable range with respect to the data. In an embodiment to be illustrated and described, the range is expressed in terms of a number of standard deviations from a given regression line. Of course, the range need not be fixed or be about a regression line. Those skilled in the pertinent art will realize that other statistical methods may be employed to advantage.
In one embodiment of the present invention, the data comprise a regression line and an acceptable range of scatter based on percent cumulative probability dropout. In the embodiment to be illustrated and described, the acceptable range of scatter is ±10units of measure.
In one embodiment of the present invention, the test circuitry develops a ratio of the corresponding intrinsic leakages. Ratios of multiple ICs manufactured by a given process normally scatter about a given line of regression. In the embodiment to be illustrated and described, this regression line is employed as a center for a given range of acceptable deviation.
In one embodiment of the present invention, the data comprise a regression line about which the scatter in paired measurements for a given device will fall within a box defined by the accuracy of the test set measurement unit employed. In an embodiment to be illustrated and described, the test limits are 2½ times the test set measurement unit accuracy. The accuracy of the test set measurement range may be determined either from the manufacturer's advertised specifications or empirically derived through statistical error-of-measurement studies. In either case, the worst-case scatter in the data-points resulting from repetitive measurements of the same device is defined by the hypotenuse of the box:
2½ * the accuracy of the test-set measurement unit. In the embodiment to be illustrated and described, defining test limits through this method is useful when auto-range measuring techniques are employed such that the measurement accuracy is range-dependent.
In one embodiment of the present invention, the differences between paired measurements will be shown to approximate a gaussian distribution centered about the ordinate or some slightly skewed non-zero number. In the embodiment to be illustrated and described, test limits may be determined through statistical methods.
In one embodiment of the present invention, the symmetrical circuits comprise a tip circuit and a ring circuit. The tip and ring circuits may form part of a
Lebo Douglas B.
Siket John M.
Washko Michael A.
Lucent Technologies - Inc.
Metjahic Safet
Sundaram T. R.
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