Statistical process window design methodology

Details Statistical process window design methodology Statistical process window design methodology

1998-08-04

2002-04-02

Grant, William (Department: 2121)

Data processing: generic control systems or specific application

Generic control system, apparatus or process

Optimization or adaptive control

C700S121000

Reexamination Certificate

active

06366822

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is directed to the mass production of semiconductor devices. The invention is more particularly directed to the problem of perceiving interactions between interrelated process steps on a mass-production line and maintaining acceptable critical dimensions across each die of a plurality of mass-produced integrated circuit wafers.
CROSS REFERENCE TO RELATED PUBLICATIONS
The following publications are cited here for purposes of reference:
(1) S. Kaplan and L. Karklin, “Calibration of Lithography Simulator by Using Substitute Patterns,”
Proceedings on Optical/Laser Mircrolitography VI,
SPIE 1927, pp. 847-858, 1993.
(2) C. Mack and E. Charrier, “Yield Modeling for Photolithography,”
Proceedings of OCG Microlithography Seminar,
pp. 171-182, 1994.
(3) TMA DEPICT,
Two
-
Dimensional Process Simulation Program for Deposition, Etching, and Photolithography, version
3.0, Technology Modeling Associates, Inc., Palo Alto, Calif., 1993.
(4) Mandel, J,
The Statistical Analysis of Experimental Data,
Chapter 12, Wiley, New York, 1964.
(5) Z. Krivokapic and W. D. Heavlin, “Predicting Manufacturing Variabilities for Deep micron Technologies: Integration of Process, Device, and Statistical Simulations,” in
Simulation of Semiconductor Devices and Processes,
5, S Selberherr, H Stippel and E Strasser, eds, pp. 229-232, Springer-Verlag, New York, 1993.
(6) W. D. Heavlin and G. P. Finnegan, “Dual Space Algorithms for Designing Space-filling Experiments,”
Interface
1994, Research Triangle, North Carolina, June 1994.
(7) B. D. Ripley, Spatial Statistics, pp. 44-75, Wiley, New York, 1981.
(8) A. B. Owen, “Controlling Correlations in Latin Hypercube Samples, ”
Journal of the American Statistical Association,
Vol. 89, No. 428, pp. 1517-1522, December 1994.
(9) W. D. Heavlin, “Variance Components and Computer Experiments,” 1994
ASA Proceedings, Section on Physical and Engineering Sciences,
Toronto, August 1994.
(10) A. R. Neureuther and F. H. Dill, “Photoresist Modeling and Device Fabrication Applications,”
Optical and Acoustical Microelectronics,
pp. 223-247, Polytechnic Press, New York, 1974.
(11) F. H. Dill, J. A. Tuttle, A. R. Neureuther, “Modeling Positive Photoresist,”
Proceedings,
Kodak Microelectronics Seminar, pp. 24-31, 1974.
(12) C. Mac, “Development of Positive Photoresists,”
Journal of the Electrochemical Society,
Vol. 134, January 1987.
(13) M. Stein, “Large Sample Properties of Simulations using Latin Hypercube Sampling,”
Technometrics,
Vol. 29, No. 2, pp. 143-151, May 1987.
(14) M. D. McKay and R. J. Beckman, “Using Variance to Identify Important Inputs,” 1994
ASA Proceedings, Section on Physical and Engineering Sciences,
Toronto, August 1994.
(15) William D. Heavlin and Luigi Capodieci, “Calibration and Computer Experiments,” 1997
American Statistical Association Proceedings, Section on Physical and Engineering Sciences,
Anaheim, August 1997 (scheduled for publication Summer 1998), pp. 58-63.
Each of the aforementioned publications is hereby incorporated by reference.
2. Description of the Related Art
Modern, high-density, integrated circuit devices are typically mass-produced with large numbers of critically-dimensioned features. In manufacturing, it is desirable to maintain the respective critical dimensions of each die within a plurality of mass-produced IC wafers constrained to certain respective values in order to assure desired operating speeds and operational characteristics of the produced IC.
Each feature on each IC die in a mass-produced wafer is the product of a succession of many process steps. Each process step is controlled by a combination of variable process parameters.
Different combinations of variations in process parameter can occur on a random basis across the numerous process steps of a mass-production line, on a die-by-die basis. This introduces noise into the uniformity of the product outflow of the production line. Sometimes a specific combination of process parameter deviations is relatively innocuous, sometimes it is not. It all depends on which process parameters are deviated for a given IC die and how their respective process steps interrelate to establish critical dimensions on that given die.
One example of such multiple, interrelated process steps that may be useful in understanding the interaction of factors in the present application, are those typically employed to define a pattern of conductive lines deposited across an insulator of an IC chip.
First, a dielectric layer of a generally non-planar form is created across the wafer. Such a non-planar dielectric layer may constitute the combined gate oxide and field oxide of a CMOS device. The non-planarity of the dielectric layer may alternatively be attributed to the non-planarity of underlying trenches, steps, mesas or other topographic features of the chip.
Next, a polysilicon or other conductive layer is deposited conformably on top of the dielectric layer. An anti-reflective coating (ARC) may be optionally deposited on the conductive layer to reduce undesired reflections in a following exposure step.
The deposition of the conductive layer and optional ARC layer is followed by a spinning-on or other deposition of a photoresist (PR) layer. The PR layer may or may not be planarized depending on process specifics.
The photoresist-coated wafer is then positioned within a stepper by an alignment mechanism. Tiled areas of the photoresist (PR) are successively exposed to a stepped pattern of resist-modifying radiation. After the step-wise exposure, the photoresist is “developed” by, for example, soft baking the wafer to induce cross-polymerization in the photoresist material and by subsequently dissolving away non-hardened portions of the photoresist with a specific solvent. The developed photoresist defines an etch mask.
The developed wafer is next etched, for example in a plasma etch chamber, so as to transfer the hardened image in the photoresist to the conductive layer. This produces a corresponding pattern of lines in the conductive (e.g., doped polysilicon) layer.
The photoresist mask is stripped off, or kept depending on process specifics, and further process steps follow. One example of a further process step is the selective implant of dopants into exposed semiconductor regions so as to create self-aligned source and drain regions at opposed sides of each conductive line, where the conductive line lies over gate oxide. The width of the conductive line at such a region of dopant implant defines the channel length of the formed IGFET transistor.
Within each of the above-described process steps, there are one or more variable physical attributes (or “process parameters”) that control the final outcome of the produced device. Some process parameters may be adjusted by a line operator. Some are “set” by the design of the process equipment that is installed into the mass-production line.
Post-exposure development time and temperature are also subject to variance away from pre-established goal values. The diffusion length of the development chemistry may vary across a wafer. In a subsequent plasma etch, the variables can include: time, pressure, temperature, flow rate, and field-proximity effects resulting from the pitch and step profile of closely spaced mask features.
Because successive steps of IC production tend to be interdependent, a slight variation in parameter(s) of one process step can be magnified by a further variation in the parameters of a second process step to produce unacceptable numbers of defective product at the output end of the mass-production line.
For example, if PR (photoresist) thicknesses decreases slightly and the focal depth of the exposure optics also decreases slightly and the exposure dosage also decreases slightly during production of a first-sampled IC chip as compared to the corresponding process parameters for a second-sampled IC chip, the combined effect may be to significantly shift the position and intensity of the radiation exposure pattern relative to the photoresist layer duri

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