Statically controlled clock source generator for VCDL clock...

Details Statically controlled clock source generator for VCDL clock... Statically controlled clock source generator for VCDL clock...

2007-12-25

2007-12-25

Kinkead, Arnold (Department: 2817)

Oscillators

Polyphase output

C331S057000, C331S074000, C327S156000, C327S158000, C327S159000, C375S376000

Reexamination Certificate

active

11221316

ABSTRACT:
The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.

REFERENCES:
patent: 7116147 (2006-10-01), Kase
“Precision CMOS Receivers for VLSI Testing Applications” A Dissertation Submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy Daniel K. Weinlader—Nov. 2001.

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