Static type semiconductor memory with latch circuit amplifying r

Details Static type semiconductor memory with latch circuit amplifying r Static type semiconductor memory with latch circuit amplifying r

1997-03-10

1998-12-15

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

365205, G11C 800

Patent

active

058503676

ABSTRACT:
A static type semiconductor memory device includes a main bit line pair, and a plurality of memory blocks connected to the main bit line pair. Each of the memory blocks includes a local bit line pair, a static memory connected to the local bit line pair, an amplifier which amplifies potential difference between the paired local bit lines, and a data transfer gate which transfers data between the local bit line pair and the main bit line pair.

REFERENCES:
patent: 4804871 (1989-02-01), Walters, Jr.
patent: 4932002 (1990-06-01), Houston
patent: 5309389 (1994-05-01), Golke et al.
patent: 5457647 (1995-10-01), McClure
patent: 5497351 (1996-03-01), Oowaki
patent: 5619466 (1997-04-01), McClure
patent: 5657286 (1997-08-01), Arimoto
patent: 5663905 (1997-09-01), Matsuo et al.
Sasaki, Katsuro, et al.: "A 9-ns 1-Mbit CMOS SRAM", Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 727-732.
Wada, Tomohisa, et al: "A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987.

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