Static timing verification in the presence of logically false pa

Details Static timing verification in the presence of logically false pa Static timing verification in the presence of logically false pa

1995-06-12

1997-07-15

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, 364491, 364578, G06F 1500, G06G 748

Patent

active

056489099

ABSTRACT:
In a method for improving a circuit having a logically false path through static analysis of a software model, a computer receives information describing the false path, determines a true path alternate to the false path, and analyses the circuit model with respect to the true path.

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