Static timing analysis of semiconductor digital circuits

Details Static timing analysis of semiconductor digital circuits Static timing analysis of semiconductor digital circuits

1988-01-28

1990-05-08

Gruber, Felix D.

Boots, shoes, and leggings

364488, 371 23, G06F 1560, G06F 1100

Patent

active

049244302

ABSTRACT:
The time verification scheme of the present invention operates without input stimulus to calculate delays along circuit paths including logic elements or cells from initial input to final output, or over sub-circuit paths, of a proposed logic design. The delay calculations include cell-dependent, and layout-dependent, and environmental-dependent factors to account for response delays on rising and falling signal; capacitance loading, temperature-dependency and voltage-dependency of a proposed logic design to provide output histograms and reports of information about overall performance, and timing violations of the proposed logic design with respect to operating parameters that can be selectively adjusted for manufacturing variations.

REFERENCES:
patent: 4263651 (1981-04-01), Donath et al.
patent: 4527249 (1985-07-01), Van Brunt
patent: 4654851 (1987-03-01), Busby
patent: 4698760 (1987-10-01), Lembach et al.
patent: 4725975 (1988-02-01), Sasaki
patent: 4744084 (1988-05-01), Beck et al.
patent: 4763288 (1988-08-01), Deering et al.
patent: 4791593 (1988-12-01), Hennion

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