Static test mode noise filter

Details Static test mode noise filter Static test mode noise filter

1993-11-30

1995-08-08

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By pulse width or spacing

327 31, 327379, 327551, H03K 908, H03K 1716

Patent

active

054401780

ABSTRACT:
According to the present invention, a time filter prevents unintentional static entry into a test mode. Static entry is delayed an appropriate period of time after receipt of the required stimulus to enter the test mode. The delay period is chosen to be longer than transient conditions present in noisy operating environments such that static entry into the test mode is not accidentally triggered. Only when a super voltage condition is applied to an integrated circuit pin for the duration of a predetermined delay time can static entry to a test mode be accomplished. Exit from a test mode occurs immediately after the stimulus is removed. Delay circuitry of the present invention comprises a plurality of transistors, a schmitt trigger, and a delay element, and the delay circuitry determines the value of the predetermined voltage level and the predetermined delay time.

REFERENCES:
patent: 4471235 (1984-09-01), Sakhuja et al.
patent: 4525635 (1985-06-01), Gillberg
patent: 5109163 (1992-04-01), Benhamida
patent: 5198710 (1993-03-01), Houston

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