Static random access memory with asynchronous power-down

Details Static random access memory with asynchronous power-down Static random access memory with asynchronous power-down

1983-08-31

1990-04-17

Gossage, Glenn A.

Static information storage and retrieval

Powering

Conservation of power

3652235, 365226, 365194, G11C 700

Patent

active

049186582

ABSTRACT:
A static random access memory, wherein power consumption is reduced by using asynchronous edge-triggered power down gates to power up only elements in the critical circuit path for only as long as necessary to access the memory. Thus, power consumption in the memory is reduced to nearly an absolute minimum. This invention uses the address transition clock to provide an asynchronous power up function to various parts of the static RAM so that only the circuit which is propagating the signal is powered up and the power is held high just long enough for the signal to propagate. This is performed using intrinsic timing elements of the RAM critical path so that the timing of the signal and power cycles track each other.

REFERENCES:
patent: 4231110 (1980-10-01), Stinehelfer
patent: 4339809 (1982-07-01), Stewart
patent: 4355377 (1982-10-01), Sud et al.
patent: 4405996 (1983-09-01), Stewart
patent: 4425633 (1984-01-01), Swain
patent: 4917328 (1983-11-01), Ochii
"4K Static RAMs Give Fast Access", Electronics, May 13, 1976, pp. 137-138, vol. 49, No. 10.
Konishi et al., "A 64 Kb CMOS RAM", IEEE International Solid State Circuits Conference, Digest of Tech. Papers, Feb. 12, 1982, pp. 258-259, 333.

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