Static random access memory (SRAM) with clamped source...

Details Static random access memory (SRAM) with clamped source... Static random access memory (SRAM) with clamped source...

2008-06-03

2008-06-03

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Powering

C365S201000, C365S154000, C365S229000

Reexamination Certificate

active

07382674

ABSTRACT:
A semiconductor memory device includes a memory cell array including a plurality of memory cells, a source terminal which supplies a source potential to the memory cells, a first switching element which electrically connects the source terminal and a first power supply potential in an operation mode of the memory cells, and electrically disconnects the source terminal and the first power supply potential in a standby mode of the memory cells, a clamp MIS transistor which is series-connected between the source terminal and the first power supply potential, and clamps the source potential in the standby mode, a bias generation circuit which supplies a first bias potential to a gate terminal of the clamp MIS transistor, and a switching circuit which switches a potential of a back gate terminal of the clamp MIS transistor between a test mode and a non-test mode.

REFERENCES:
patent: 6999338 (2006-02-01), Hirabayashi
patent: 2004/0227542 (2004-11-01), Bhavnagarwala et al.
Masanao Yamaoka, et al. “A 300MHz 25 μA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage Active Mode for Mobile-Phone Application Processor”, 2004 IEEE International Solid-State Circuits Conference, Feb. 18, 2004, 10 pages.
Y. Takeyama, et al. “A Low Leakage SRAM Macro with Replica Cell Biasing Scheme”, 2005 Symposium on VLSI Circuits Digest of Technical Papers, 2005, pp. 166-167.
U.S. Appl. No. 11/219,827, filed Sep. 7, 2005, Osamu Hirabayashi.

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