Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-02-21
2002-04-02
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S189020, C365S154000
Reexamination Certificate
active
06366526
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to memory management and storage in a computer or other system that uses static random access memory (SRAM), and more particularly, to a distributed decode system and method for improving SRAM density.
BACKGROUND OF THE INVENTION
A typical random access memory (RAM; e.g., static RAM (SRAM) or dynamic RAM (DRAM)) system for a computer includes an array with one or more columns of SRAM cells configured to store respective logic states, ie., either a logic high (logical “1”) or a logic low (logical “0”). Data is written to and/or read from each of the SRAM cells in each column via differential complimentary bit and nbit connections. An address wordline, which is decoded from a computer address sent by a central processing unit (CPU) or other processor, is communicated to the SRAM cells. The address wordline particularly identifies and enables a specific SRAM cell during each reading and writing operation.
A write driver is designed to write data to a specific SRAM cell that is identified by an address wordline. The bit and nbit connections are initially precharged. In order to write a logic state to a particular SRAM cell, the write driver discharges one of the bit and nbit connections while maintaining the state of the other, in order to create a voltage differential between the connections and instill a particular logic state in the SRAM cell.
A sense amplifier is utilized to retrieve data from SRAM cells. The sense amplifier is typically a differential amplifier. It receives the differential complimentary signals on the bit and nbit connections and can read the stored logic state based upon the voltage differential and polarity between the connections. The sense amplifier produces a data output when prompted to do so by a strobe control signal. The strobe control signal can be a clock edge generated by some type of a timing control unit.
In order to create high-density memories requiring little space, storage elements are often made with the fewest and smallest parts possible. A problem exists, however, in that a high number of decoders are required to access the desired address wordline and column to enable a specific SRAM cell in the array. The use of the large number of decoders imposes a substantial size and component count burden on the chip. Moreover, because the arrays of memory cells in these types of configurations are large, the decoders that are required to drive signals across the arrays to overcome the resistance of the signal wires must also be large. This configuration requires large decoders to maintain the “sweet spot” which is commonly known as the optimal relationship between the resistance of the signal wires to the size of the driver that is required to overcome the resistance. Consequently, the large number of decoders required to properly address the multitude of SRAM cells combined with the requirement that the decoders themselves must be large to maintain the sweet spot, the number of SRAM cells that can be placed on a single chip is substantially limited.
In order to improve the density of SRAM cells relative to speed, a heretofore unaddressed need exists in the industry for an improved SRAM system that increases speed and reduces size and the number of required components in the chip.
SUMMARY OF THE INVENTION
An object of the invention is to overcome the deficiencies and inadequacies of the prior art, as described previously in the background section. Briefly described, the present invention provides for distributed decode system and method for improving static random access memory (SRAM) density.
With respect to architecture, the system is implemented as follows. The system includes a plurality of groups of memory cells. The groups of memory cells are comprised of first and second pluralities of memory cell columns whereby each of the columns include at least one memory cell. The individual memory cells are configured to read and write a respective logic state. The system further includes a sense amplifier in each of the groups, and it is coupled between the first and second pluralities of memory cell columns. A column multiplexer is included in each of the groups of memory cells and is coupled to the first and second pluralities of memory cell columns and the sense amplifier. Additionally, the system includes a global decoder centrally coupled to the groups of memory cells, and it is configured to select any individual said memory cell in any of the groups of memory cells according to an address instruction executed by said global decoder.
In an alternative embodiment, the system is implemented with plurality of groups of memory cells. The groups of memory cells are comprised of first and second pluralities of memory cell columns whereby each of the columns include at least one memory cell. The individual memory cells are configured to read and write a respective logic state. The system receives an address instruction information in a global decoder. The global decoder is centrally located in the plurality of memory cell groups. The system enables one of the plurality of groups of memory cells from the global decoder in response to the address instruction information. From the global decoder and in response to the address instruction information, the system activates a local wordline decoder and a local column decoder, which are both contained in the enabled memory cell group. The activated local wordline decoder is implemented to enable a wordline contained in the enabled memory cell group, and the activated local column decoder is implemented to enable a memory cell column contained in the enabled memory cell group. A specific logic state is either read from or written to a memory cell coupled to the enabled wordline and contained in the enabled memory cell column.
The invention has numerous advantages, a few of which are delineated hereafter, as merely examples.
An advantage of the invention is that it improves the speed of SRAM designs by requiring a fewer number of blocks through which to route signals.
Another advantage of the invention is that the density of the memory cells on the SRAM chip is greater because the invention minimizes the number of components required for implementation of a SRAM, particularly, significantly reducing the number of decoders required to access each individual SRAM cell.
Another advantage of the invention is that it is simple in design, reliable in operation, and easily implemented in mass production.
Other objects, features, and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional objects, features, and advantages be included herein within the scope of the present invention, as defined by the claims.
REFERENCES:
patent: 5765214 (1998-06-01), Sywyk
patent: 6044028 (2000-03-01), Tomohiro et al.
patent: 6072735 (2000-06-01), Komoriya et al.
Naffziger Samuel D
Weiss Donald R
Wuu John
Ho Hoai V.
Nelms David
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