Static random access memory dynamic address decoder with non-ove

Details Static random access memory dynamic address decoder with non-ove Static random access memory dynamic address decoder with non-ove

1995-06-23

1997-01-28

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365233, 36523008, 326105, G11C 800

Patent

active

055983758

ABSTRACT:
An address decoder having non-overlapping word line enable is disclosed having a dynamic logic gate-based decoding section. The decoder includes a deadtime signal generator that produces a pulse at the rising edge of every input clock cycle. The decoder further includes a transmission gate responsive to the deadtime signal for selectively passing the decoder section output signal to a latch. The decoder further includes a NOR logic having an output for coupling to a memory word line which is gated by the deadtime signal to disable the output while the transmission gate passes the decoder output to the latch. When the deadtime pulse transitions to a low state, the latch captures the decoder output signal and enables the output of the NOR gate.

REFERENCES:
patent: 4156291 (1979-05-01), Baker
patent: 4916668 (1990-04-01), Matsui
patent: 4984215 (1991-01-01), Ushida

Affiliated with

Also associated with

Rating

Static random access memory dynamic address decoder with non-ove does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Static random access memory dynamic address decoder with non-ove, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Static random access memory dynamic address decoder with non-ove will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-945637