Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
1999-03-03
2001-09-18
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S758000, C257S903000, C257S904000
Reexamination Certificate
active
06291883
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a semiconductor device and, more specifically, to a semiconductor and a method of manufacture therefore wherein the semiconductor has a static random-access memory with a local conductive layer incorporated therein.
BACKGROUND OF THE INVENTION
Static random-access memory devices (SRAM) are well known and used extensively in semiconductor devices, such as complementary metal oxide semiconductors (CMOS). Static memories do not require periodic refresh signals in order to retain their stored data. The bit state in SRAM is stored in a pair of cross-coupled invertors, which form a circuit known as a flip-flop. The voltage on each of the two outputs of a flip-flop circuit is stable at only one of two possible voltage levels, because the operation of the circuit forces one output to a high potential, and the other to a low potential. The memory logic state of the cell is determined by whichever of the two inverter outputs is high. Flip-flops maintain a given state for as long as the circuit receives power, but they can be made to undergo a change in state (i.e., to flip), through the application of a trigger voltage of sufficient magnitude and duration to the appropriate input. Once the circuit has settled into its new stable state, the trigger voltage can be removed. SRAM cells can be implemented in NMOS, CMOS, bipolar or BICMOS technologies. For a more general background on this subject, see S. Wolf,
Silicon Processing for the VLSI Era,
Vols. I, II, and III, Latice Press, which are incorporated herein by reference.
The chief disadvantage of an SRAM cell is that it consists of at least six devices, as compared to only two for the dynamic-memory cell (DRAM). Thus, even when the same set of design rules is used, an SRAM chip cannot be built with as many cells as a DRAM chip in the same amount of area. One reason for the size of the SRAM is that separate openings or interconnect structures are used to connect to the silicon in the substrate and to the gate. Due to design rules, the interconnect structure must be a certain distance from the gate to prevent any possible short to the gate during the interconnects formation down to the silicon. These same design rules also cause the overall size of the SRAM cell to remain larger than desired.
On the other hand, SRAMs are the fastest semiconductor memories. Their speed is derived from the self-restoring nature of the flip-flop and the static peripheral circuits of the memory chip. Bipolar SRAMs are the fastest of all, and MOS SRAMs are the fastest among MOS memories.
Because of their speed, SRAMs use in devices that typically use DRAM cells is highly desirable. Unfortunately, however, it is also highly desirable to decrease the overall size of the device. Thus, conventionally designed SRAMs are often not used because the need for a smaller device outweighs the need for a faster device.
Accordingly, what is needed in the art is a device and method of manufacture thereof that provides a smaller SRAM cell. The device and method of the present invention address this need.
SUMMARY OF THE INVENTION
The present invention provides a static random-access memory (SRAM) device that comprises a substrate having a gate formed thereover, where the gate is insulated from the substrate, and a local conductive layer that is formed over the substrate and contacts an electrical structure within the SRAM device. The local conductive layer further contacts the gate to connect the gate electrically to the electrical structure. The SRAM device, in one embodiment, is part of a complementary metal oxide semiconductor (CMOS) or an N-channel metal oxide semiconductor (NMOS). However, it will be appreciated by those who are of ordinary skill in the art that the present invention may be used in various types of metal oxide semiconductors and various devices that employ those semiconductors.
The present invention therefore provides, in one embodiment, a local conductive interconnect structure that provides an electrical path to which the gate may be electrically connected to other portions of the SRAM device without the need of multiple interconnect structures found in prior art devices. Since an aspect of the present invention provides this option, the overall cell size of the SRAM device may be substantially decreased such that it can be used in applications that require smaller cell sizes.
In another embodiment, the local conductive layer is comprised of a conductive metal. For example, the local conductive layer may comprise a layer of titanium having a layer of titanium nitride formed over it that contacts the titanium layer. It will, of course, be apparent that other conductive materials that are used for fabricating such devices may be used in place of the titanium or titanium nitride. In those embodiments where the conductive layer is formed from titanium and titanium nitride, the titanium layer may be about 20 nm thick and the titanium nitride layer may have a thickness that ranges from about 60 nm to about 80 nm.
In one embodiment, the local conductive layer terminates on silicon, that is, the local conductive layer stops on an area that is in contact with the silicon substrate. In one advantageous embodiment, the local conductive layer terminates over the p-channel transistor.
In yet another embodiment, the SRAM device further comprises an oxide layer that is formed over and that contacts the local conductive layer. The oxide layer is patterned and etched such that it has common end edges with the local conductive layer.
In another embodiment, the local conductive layer is connected to the conductive interconnect structure by a single path. In one aspect of this particular embodiment, the single path is a conductive interconnect structure that includes an opening formed in a substrate dielectric layer that is formed over the gate. The opening has an interconnect conductive layer formed therein that contacts a portion of the local conductive layer to connect the local conductive layer electrically to the gate.
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Lee Kuo-Hua
Nagy William J.
Agere Systems Guardian Corp.
Eckert II George C.
Lee Eddie
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