Static random access memory capable of preventing erroneous writ

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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365194, G11C 700, G11C 800

Patent

active

053574796

ABSTRACT:
Memory cell arranged in a matrix configuration are selected by a particular word line to supply the stored data to particular bit lines. The row address decoder selects a particular word line based on the address signal, while the column address decoder selects particular bit lines based on the address signal. Each of the row address decoder and column address decoder contains a first decoder for decoding the address signal, a delay circuit for delaying the output from the first decoder when data is written into the memory cell, and a second decoder for receiving the output signals from the first decoder and delay circuit and based on these signals, selecting either a particular word line or particular bit lines.

REFERENCES:
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patent: 4768168 (1988-08-01), Watanabe
patent: 4803665 (1989-02-01), Kasa
patent: 4849937 (1989-07-01), Yoshimoto
patent: 4931998 (1990-06-01), Ootani et al.
patent: 4985865 (1991-01-01), Houston
patent: 5062082 (1991-10-01), Choi
patent: 5091889 (1992-02-01), Hamano et al.

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