Static random access memory

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Patent

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Details

365154, 36518901, G11C 1300

Patent

active

050704826

ABSTRACT:
A static RAM in which the threshold voltage of the drive transistors of a memory cell is higher than the threshold voltage of the access transistors, and in which the impedance of the access transistors is lower during writing then during reading, for improving data retention properties of the memory cell. The bit or data lines for reading data from the memory cell is provided with an equalizing circuit and data writing is performed from a writing buffer circuit. This writing buffer circuit is controlled by a pulse generator generating a pulse of a constant predetermined width on the basis of detected address transition to maintain a constant cycle time duration even on the occasion of a continuous write operation.

REFERENCES:
patent: 4961172 (1990-10-01), Shubat et al.

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