Static random access memory

Details Static random access memory Static random access memory

1998-01-27

1999-08-10

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Plural blocks or banks

365190, 365203, 365233, 365236, G11C 700

Patent

active

059369094

ABSTRACT:
A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address selection circuit selects a memory cell in one of the memory mats, and connects the selected memory cell to a sense amplifier or a write amplifier furnished corresponding to the memory mat in question. At the same time, an address counter generates an address signal corresponding to the address signal by which one of the memory mats has been selected. When a burst mode is designated by a control signal, the address signal admitted to the address register is used to select a memory cell in a first memory mat. The selected memory cell is connected to the corresponding sense amplifier or write amplifier. Then in accordance with the address signal generated by the address counter, a memory cell in another memory mat is selected and connected to the corresponding sense amplifier or write amplifier.

REFERENCES:
patent: 4893278 (1990-01-01), Ito
patent: 5150325 (1992-09-01), Yanagisawa et al.

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