Static RAM cell with soft error immunity

Details Static RAM cell with soft error immunity Static RAM cell with soft error immunity

1990-09-28

1991-10-15

Prenty, Mark

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 51, 365154, 365182, H01L 2702, G11C 1100, G11C 1134

Patent

active

050578936

ABSTRACT:
An integrated circuit device structure for a static random access memory includes a feature which improves soft error immunity. Each static random access memory has two storage nodes for storing data of that cell. Each of these nodes is at the connection of the drain of a pull-down transistor and the source-drain of a pass transistor which occurs in a doped region of the substrate in which the integrated circuit is formed. The soft error immunity is increased by increasing the capacitance of each of the storage nodes. This is achieved by providing only a thin insulating layer over the doped regions of the storage nodes and extending a portion of grounded, heavily-doped polysilicon over the doped regions. The ground polysilicon is then separated from the doped regions by only the thin insulating layer so there is thus substantial added capacitance to the storage nodes.

REFERENCES:
patent: 4849801 (1989-07-01), Honjyo et al.

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