Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Patent
1992-07-22
1993-05-11
Hille, Rolf
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
257369, 257393, 257903, H01L 2904, H01L 2978
Patent
active
052104290
ABSTRACT:
A static RAM cell including first and second bulk transistors having gate electrodes extended over an element isolation region and forming a flip-flop, third and fourth bulk transistors having source and drain regions and formed adjacently to the element isolation region, a first conductive strap layer for self-aligning the gate electrode of the first bulk transistor with the source or drain region of the third bulk transistor, and a second conductive strap layer for self-aligning the gate electrode of the second bulk transistor with the source or drain region of the fourth bulk transistor.
REFERENCES:
patent: 4453175 (1984-06-01), Ariizumi et al.
patent: 4774203 (1988-09-01), Ikeda et al.
patent: 4792841 (1988-12-01), Nagasawa et al.
patent: 4984200 (1991-01-01), Saitoo
patent: 5057898 (1991-10-01), Adan et al.
Patent Abstracts of Japan, vol. 13, No. 404 (E-817) Sep. 7, 1989 and JP-A01 144 655, Jun. 6, 1989.
Patent Abstracts of Japan, vol. 13, No. 404 (E-817) Sep. 7, 1989 and JP-A-1144674 (Hitachi) Jun. 6, 1989.
Pat. Abs. of Japan, vol. 13, No. 433 (E-824) Sep. 27, 1989 and JP-A-1161860 (Hitachi) Jun. 26, 1989.
Int'l Electron Devices Meeting, Dec. 1888, San Francisco, Calif., pp. 48-51; T. Yamanaka et al.: `A 25 UM2 New Poli-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity`.
Hille Rolf
Limanek Robert
Sharp Kabushiki Kaisha
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