Static MOS super buffer latch

Details Static MOS super buffer latch Static MOS super buffer latch

1986-07-29

1988-06-28

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307448, 307450, 307291, H03K 326, H03K 1716, H03K 19017, H03K 329

Patent

active

047541652

ABSTRACT:
A low-power high-speed static latch with super buffer outputs is implemented as an MOS integrated circuit by providing resistive cross coupling from those super buffer outputs to inputs through depletion devices that serve in the place of high valued resistors. The resulting static latch exhibits only one gate delay from input to output, has only one enhancement device at a time on, and may be used to create a static MOS shift register.

REFERENCES:
IBM Tech. Disc., Dailey et al., vol. 13, No. 8, Jan. 1971.

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