Static memory with self aligned contacts and split word lines

Details Static memory with self aligned contacts and split word lines Static memory with self aligned contacts and split word lines

1993-02-02

1994-10-25

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257776, 257903, 257393, 257401, 365182, H01L 2348, H01L 2702, G11C 1134

Patent

active

053592263

ABSTRACT:
A compact static random access memory is formed using both split word lines and self aligned contacts. Self aligned contacts between gates of the pull-down transistor and cross-couple interconnects decreases the critical spacing between elements of the cell and permit the cell to be smaller or more manufacturable. The use of split word lines allows memory cell connections to the bit lines to be located on opposite sides of a memory cell. The connections are widely separated along a direction parallel to the bit lines so perpendicular separation between the bit lines can be decreased. The split word lines also allow the memory cell lay out to be symmetric and thereby increases stability. Use of self aligned contacts further decreases the necessary separation between the bit lines. A further feature is a straight conductor which runs though the center of the memory cell and connects the source of the pull-down transistors to a reference voltage V.sub.SS.

REFERENCES:
Itabashi, et al., IEDM Tech. Dig., pp. 477-480, 1991.
Ohkubo, H., et al., IEDM Tech. Dig., pp. 481-484, 1991.
Matsumiya, et al., IEEE Journal of Sol. St. Cir., vol. 27, No. 11, Nov., 1992.
Sasaki, et al., IEEE Journal of Sol. St. Circ., vol. 27, No. 11, Nov., 1992.

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