Static memory having pipeline registers

Details Static memory having pipeline registers Static memory having pipeline registers

1990-03-05

1992-03-03

Popek, Joseph A.

Static information storage and retrieval

Addressing

Plural blocks or banks

365233, 364DIG2, 395425, 395800, G11C 700

Patent

active

050938096

ABSTRACT:
Static memory having pipeline registers. The static memory has a plurality of hierarchy levels connected by pipeline registers. This architecture is very beneficial since the area requirements for the drive and read-out circuits in the first hierarchy level are especially critical. Advantageously, memory cells are used which have write and read word lines as well as separate write and read data lines and which also supply a strong cell signal so that only a few components are needed for the read circuit. A new clock format with an arrangement of pipeline registers is proposed for the appertaining memory for which power consumption is reduced by disconnecting the clocks in the lower hierarchy levels, resulting in increased area savings.

REFERENCES:
patent: 4633440 (1986-12-01), Pakulski
"256.times.4 Bit Registered Self-Timed Static RAM 2.5 ns Cycle Time", Giga Bit Logi Inc., May 1988, pp. 2-2.
CMOS Data Book, "Advanced Information Self-Timed Pipeline Static RAMs", Cypress Semiconductors, 15 Jan. 1988, pp. 2-83.
"Principles of CMOS-VLSI-Design", Addison Wesley, Reading, MA, 1985, Chapter 5.4.

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