Static memory having load polysilicon resistors formed over driv

Details Static memory having load polysilicon resistors formed over driv Static memory having load polysilicon resistors formed over driv

1984-01-19

1985-09-10

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 237, 357 239, 357 51, 357 59, 365154, 365182, H01L 2704, G11C 1140

Patent

active

045410062

ABSTRACT:
A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected respectively in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above the drain of the first insulation gate FET transistor, and the second polycrystalline silicon layer is provided above the drain of the second insulation gate FET transistor.

REFERENCES:
patent: 4110776 (1978-08-01), Rao et al.
patent: 4125854 (1978-11-01), McKenny et al.
patent: 4240097 (1980-12-01), Raymond, Jr.
patent: 4322824 (1982-03-01), Allan
patent: 4326213 (1982-04-01), Shirai et al.
patent: 4352997 (1982-10-01), Raymond, Jr. et al.
patent: 4453175 (1984-06-01), Ariizumi et al.
"A 2K.times.8-Bit Static RAM", T. Ohzone et al., IEEE IEDM, Tech. Digest, pp. 360-363 (Dec. 3, 1978).

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