Static memory cell with inverted field effect transistor

Details Static memory cell with inverted field effect transistor Static memory cell with inverted field effect transistor

1977-05-31

1979-02-13

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307304, 357 42, 357 59, 365178, 365181, 365182, 365188, G11C 1140, H03K 3353

Patent

active

041397851

ABSTRACT:
An integrated semiconductor memory device of the static type uses a memory cell circuit having an MOS transistor of the conventional type as the access transistor, along with a resistance element buried under field oxide and an inverted field-effect transistor formed by a polycrystalline layer over a gate region. The MOS transistor connects a storage node to the access line, and the inverted field-effect transistor connects the storage node to reference potential. The storage node is connected to a second node through the resistance element, and a resistor connects the second node to a voltage supply; the magnitude of the resistance element varies according to the voltage on the storage node. The impedance of the inverted field-effect is determined by the voltage on the second node which is a moat region forming the gate.

REFERENCES:
patent: 3593037 (1971-07-01), Hoff, Jr.
patent: 3618053 (1971-11-01), Hudson et al.
patent: 3699544 (1972-10-01), Joynson et al.
patent: 3744037 (1973-07-01), Spence
patent: 3997881 (1976-12-01), Hoffmann
patent: 4000427 (1976-12-01), Hoffmann
patent: 4044342 (1977-08-01), Suzuki et al.
patent: 4055444 (1977-10-01), Rao
patent: 4060796 (1977-11-01), Togei et al.
patent: 4070653 (1978-01-01), Rao et al.

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