Static memory cell having independent data holding voltage

Details Static memory cell having independent data holding voltage Static memory cell having independent data holding voltage

2002-04-16

2002-10-22

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Powering

Conservation of power

C365S228000, C365S226000, C365S156000, C365S154000, C257S393000

Reexamination Certificate

active

06469950

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor integrated circuit that is operated at a low voltage and which employs a static memory cell composed of MIS (metal insulator semiconductor) or MOS (metal oxide semiconductor) transistors (hereafter, “MOS transistors”). More particularly, the present invention relates to a circuit suited for a high-speed/low-power static memory, such as SRAM (static random access memory).
A gate-insulated field-effect transistor, such as a MOS transistor, requires an operating voltage that decreases as the transistor size decreases, because the breakdown voltage of the transistor decreases with the smaller size. As well, the threshold voltage (VT) of the MOS transistor must be lowered in accordance with the drop of operating voltage so as to retain high-speed operation, because the operating speed is dominated by the effective gate voltage of the MOS transistor (i.e., the operating voltage minus VT), and increases as the difference increases.
Generally speaking, however, if the VT is lower than about 0.4 V, a direct subthreshold current, which exponentially increases with the drop in VT, will flow through the MOS transistor which should intrinsically be cut off. As a result, the direct current greatly increases in a semiconductor integrated circuit composed of a number of MOS transistors, even if the circuit is a CMOS circuit. Hence, the direct current is a significant problem for future semiconductor integrated circuit design, in which high speed, low power consumption, and low voltage operation are important. Specifically, the subthreshold currents accumulate to establish the large direct current in the entire chip. Thus, the VT of the cross-coupled transistors of the static memory cells cannot be reduced below about 0.4 V. Therefore, the effective gate voltage can only decrease as the operating voltage decreases. As a result, the margin of the memory cells is narrowed or the operating speed is lowered, becoming more susceptible to influences of VT variation during fabrication, caused by dispersion.
FIG. 2
shows a memory cell for illustrating the problems of the prior art, and a waveform timing chart for explaining these problems in more detail.
The memory cell of
FIG. 2
is exemplified by a CMOS-type static memory (SRAM). The memory cell is said to be “inactivated” when data are stored such that a word line (WL) is at a low level of 0 V, a data storage node N
2
in the cell is at a high level equal to the supply voltage VCC of 1 V, and another data storage node N
1
is at a low level of 0 V. In the prior art, the threshold voltage VT of all transistors of the memory cell is greater than 0.4 V so that both an N-channel MOS transistor QS
2
and a P-channel MOS transistor QC
1
are off, because the voltage between the gates and sources of QS
2
and QC
1
is 0 V. The current flowing through the VCC terminal can thus be neglected, which is why the SRAM is considered to be “low power”.
The voltage margin of this memory cell becomes smaller as the difference (VCC−VT) becomes smaller. Thus, the VT must be decreased for a lower VCC. As the VT is lowered below 0.4 V, however, the subthreshold current flows through transistors QS
2
and QC
2
, which should be intrinsically off, and so the subthreshold current exponentially increases as VT decreases. Generally speaking, the VT will disperse with the fluctuation of the fabrication process, and the subthreshold current will increase for higher temperatures. This current will further increase if both the VT dispersion and junction temperature increase are considered.
Moreover, since the subthreshold current flows through all of the memory cells in the chip, a total current as high as 10 mA or larger may flow through an SRAM of, for example, about 128 Kbits. This current is also the data holding current for the entire cell array. This is a serious problem, considering that the data holding current of the ordinary SRAM using MOS transistors having a relatively high threshold voltage so as to suppress the subthreshold current substantially can be made less than 10 &mgr;A. To prevent this high aggregate current, therefore, the VT has been set at a relatively high level of 0.4 V or higher.
Some consideration is also given to lowering the VCC, with the VT fixed at 0.5 V, for example. The demand for dropping the VCC comes not only from the low breakdown voltage of the MOS transistors, but also from low power consumption, or drive by a single battery. If the miniaturization of MOS transistors advances so that the channel length is less than 0.5 &mgr;m, or that the gate insulator has a thickness of less than 6 &mgr;m, the transistor can operate at a sufficiently high speed even with an external supply voltage VCC as low as 1.5 to 1.0 V. Thus, the voltage VCC can be lowered to that extent, with preference given to lower power consumption.
Dropping the VCC, however, decreases seriously the voltage margin of the memory cell, because the effective gate voltage of the conducting transistor QS
1
is “VCC−VT”, so that the effective gate voltage becomes smaller as the VCC comes closer to VT. This drastically increases the fluctuation ratio of the VT to the dispersion. Moreover, the conventional protection against soft errors will drop together with the margin of the threshold voltage difference (offset voltage) between the cross-coupled paired transistors (QS
1
and QS
2
, QC
1
and QC
2
) in the memory cell to the equivalent noise.
When the memory cell is “activated”, speed or operation margin is also reduced if the VT is as high as 0.5 V, with a low VCC. If a VCC of 1 V, for example, is applied to the word line WL, transistors QT
1
and QS
1
are turned on, so that a small voltage change of 0.2 V is caused by the current flowing through the transistors and the load resistor (composed of MOS transistors) connected to a data line DL. On the other hand, transistor QS
2
has a gate voltage that is far lower than the VT and is off, so that no voltage change appears in the other data line /DL. By the voltage polarity of this data line pair, the stored data of the memory cell are discriminated and read out. This discrimination is more stable for a larger change in the voltage appearing on the data line DL. Such a large voltage change requires a high and constant current to flow through QS
1
and QT
1
. However, this current becomes lower as the VCC drops because QS
1
and QT
1
have substantially equal effective gate voltages of (VCC−VT), and is seriously influenced by the dispersion of the VT.
As described above, the circuit and drive system of the prior art suffers from an extreme increase of the direct current, a drop/fluctuation of operating speed, or a drop in operation margin, as the VCC drops. As a result, the performance of the SRAM chip or microprocessor chip containing an SRAM is seriously deteriorated as the VCC drops.
SUMMARY OF THE INVENTION
An object of the present invention is to suppress the increase in the subthreshold current and the drop of the voltage margin caused by the low voltage operation of the cross-coupled MOS transistor static memory cell, in a static memory or semiconductor integrated circuit in which the static memory is incorporated.
This object can be realized by controlling the voltage of at least one power supply line of a static memory cell having cross-coupled MOS transistors which conduct no substantial current between their drains and sources, even if the gate and source voltages are equal. The voltage difference between the two data storage nodes in the inactivated memory cell may exceed the voltage difference between the two data storage nodes of the cell when a voltage corresponding to write data is applied from the data line pair to the data storage nodes of the memory cell when activated. As a result, the voltage between the two data storage nodes in the memory cell can be made sufficiently high even if the main supply voltage is low when the memory cell is activated, so that the memory cell can be stably operated w

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